LCD Gate Driver Clock Signal Generator with Intermediate Voltage
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Solution Overview
Problem
Liquid crystal display (LCD) image quality is deteriorated by kickback voltage, and existing methods for improving it, such as charge sharing, are insufficient in reducing power consumption and noise.
Innovation Solution
A driving apparatus for LCDs that includes a signal controller, a clock signal generator, and a gate driver, which generates clock signals with a voltage swinging between a high, an intermediate, and a low voltage, using switches and a voltage generator with resistors and operational amplifiers to control the voltage levels and sharing, thereby reducing kickback voltage and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If charge sharing method is used to improve image quality, then kickback voltage deterioration is reduced, but power consumption reduction is insufficient
Solution Approach 1:
The clock signal voltage transition is segmented into two stages: first from high voltage to intermediate voltage, then from intermediate voltage to low voltage. This segmentation extends the charge sharing time by creating an intermediate state, allowing more complete charge transfer between high and low voltage sides, thereby improving image quality while enabling better power consumption reduction through optimized transition timing.
Solution Approach 2:
An intermediate voltage level is introduced as a mediator in the clock signal transition process. This intermediate voltage serves as a transitional state that facilitates smoother charge sharing between high and low voltage sides, extending the charge sharing time and improving both image quality and power consumption efficiency by avoiding direct high-to-low voltage transitions.
2Reliability
If charge sharing method is used to improve image quality, then kickback voltage deterioration is reduced, but noise is not efficiently reduced
Solution Approach 1:
The clock signal transition is divided into segmented stages with an intermediate voltage level, extending the transition time. This segmentation allows noise filtering to occur during the intermediate state, as the prolonged transition period enables better stabilization and reduces high-frequency noise components, thereby improving image quality while effectively reducing noise.
3Device complexity
If conventional clock signal with direct voltage transition is used, then circuit complexity is low, but kickback voltage causes image quality deterioration
Solution Approach 1:
An intermediate voltage level is introduced as a mediator in the clock signal path. This intermediary state extends the charge sharing time by creating a two-stage transition (high to intermediate, then intermediate to low), which effectively reduces kickback voltage and improves image quality while maintaining relatively simple circuit implementation through additive circuit components.
Data Source
AI summary
A driving apparatus for a display device includes: a signal controller that generates a pre-clock signal, a charge sharing control signal and a scanning start signal; a clock signal generator that generates a clock signal swinging between a first voltage and a second voltage based on the pre-clock signal and the charge sharing control signal; and a gate driver that generates gate signals based on the scanning start signal and the clock signal, where the clock signal generator includes: a voltage generator that generates a third voltage; and a clock generator that receives one of the first to third voltages in response to the pre-clock signal and the charge sharing control signal, and outputs an output signal based on the one of the first to third voltages as the clock signal, where the third voltage is lower than the first voltage and higher than the second voltage.