LCD Gate Driver Dummy Insertion Period for Display Unevenness
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Solution Overview
Problem
In liquid crystal display devices, particularly in multi-pixel drive systems, the polarity inversion cycle of data signals can vary, leading to disparities between the data signal and retention capacitor signal, causing display unevenness due to waveform rounding, especially when inverting polarity, which affects charging rates and image quality.
Innovation Solution
The liquid crystal display device incorporates scanning signal lines divided into blocks with odd and even groups, where scanning signal lines are interlace-scanned, and data and retention capacitor signals are switched with predetermined timing, including a dummy insertion period after polarity inversion to synchronize polarity inversion timing across frames, ensuring equal polarity inversion cycles and reducing display unevenness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multi-pixel drive is used to improve viewing angle dependency in gamma characteristic, then display quality is improved, but display unevenness occurs due to waveform rounding when inverting polarity
Solution Approach 1:
The patent applies preliminary action by inserting a dummy horizontal period before the polarity inversion of data signals. This dummy period allows the liquid crystal capacitance to be charged in advance with a stable voltage level before the actual data signal polarity inversion occurs. By performing this charging action beforehand, the system avoids the waveform rounding problems that would occur if data signals were written immediately during or after polarity inversion, thus eliminating display unevenness while maintaining the multi-pixel drive functionality for improved viewing angle dependency.
2Reliability
If polarity inversion is performed to prevent liquid crystal element deterioration, then device reliability is improved, but display unevenness occurs due to waveform rounding
Solution Approach 1:
The patent applies preliminary action by inserting a dummy horizontal period before the polarity inversion of data signals. This dummy period allows the liquid crystal capacitance to be charged in advance with a stable voltage level before the actual data signal polarity inversion occurs. By performing this charging action beforehand, the system avoids the waveform rounding problems that would occur if data signals were written immediately during or after polarity inversion, thus eliminating display unevenness while maintaining the multi-pixel drive functionality for improved viewing angle dependency.
3Manufacturing precision
If data signal polarity is inverted to maintain image quality, then display quality is improved, but charging rate of pixels decreases due to waveform rounding
Solution Approach 1:
The patent applies preliminary action by inserting a dummy horizontal period before the polarity inversion of data signals. This dummy period allows the liquid crystal capacitance to be charged in advance with a stable voltage level before the actual data signal polarity inversion occurs. By performing this charging action beforehand, the system avoids the waveform rounding problems that would occur if data signals were written immediately during or after polarity inversion, thus eliminating display unevenness while maintaining the multi-pixel drive functionality for improved viewing angle dependency.
Data Source
AI summary
A gate driver creates a dummy insertion period in which the driver does not apply a gate on pulse to a scanning signal line immediately after the time of the inversion of a data signal. When a period from the time of the application of the gate on pulse to an odd numbered or even numbered scanning signal line to which the gate on pulse is applied previously to the time of the application of the gate on pulse to an even numbered or odd numbered scanning signal line to which the gate on pulse is applied later is set as an adjacent line writing time lag period for two scanning signal lines adjacent to each other, a CS control circuit allows the polarity of every CS signal to be reversed on the same cycle at least in the adjacent line writing time lag period.