LCD Gate Driver Flicker Reduction via Segmented Signal Modulation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing liquid crystal display (LCD) devices suffer from display quality degradation due to erroneous gate signal modulation, leading to flicker and non-uniform brightness, particularly in double pixel gate in panel (DGIP) type LCDs, where gate signal modulation in the front portion of the turn-on time section causes brightness reduction and display quality deterioration.
Innovation Solution
A method of driving a liquid crystal display device that involves generating and modulating gate signals using first and second flicker signals with a time difference of half a period, adjusting the voltage values of the gate signals to reduce pixel voltage differences and prevent flicker, by integrating a gate driver with pulse width modulation and level shifter components to ensure uniform brightness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If gate signal modulation is applied to reduce pixel voltage differences, then display uniformity is improved, but flicker and brightness reduction occur in the front portion of the turn-on time section
Solution Approach 1:
The gate signal modulation is segmented into different time portions: the front portion of the turn-on time section is excluded from modulation to prevent flicker, while the rear portion is modulated to reduce pixel voltage differences. This temporal segmentation resolves the contradiction by applying modulation only where beneficial.
Solution Approach 2:
Different portions of the gate signal are treated with different modulation characteristics. The front portion maintains original characteristics to avoid flicker, while the rear portion applies voltage adjustment to improve display uniformity. This local differentiation resolves the contradiction by optimizing each portion for its specific function.
2Device complexity
If double pixel gate in panel (DGIP) structure is used, then device complexity is reduced, but display quality deterioration occurs due to erroneous gate signal modulation
Solution Approach 1:
The gate driver dynamically adjusts gate signal voltages based on temporal position within the frame period. By making the modulation dynamic and adaptive to the specific timing context, the system maintains display quality while utilizing the simplified DGIP structure.
Solution Approach 2:
The gate driver incorporates feedback mechanisms to monitor and adjust gate signal voltages, ensuring that modulation is applied correctly to reduce pixel voltage differences without causing display quality deterioration. This feedback control resolves the contradiction between simplified structure and maintained quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents display quality deterioration, such as flicker, and improves brightness uniformity by adjusting the gate signal modulation to reduce pixel voltage differences, thereby enhancing the overall display quality.
Implementation Method 1
An LCD device relies on optical anisotropy and polarizability of liquid crystal molecules to produce an image
Implementation Method 2
An LCD device relies on optical anisotropy and polarizability of liquid crystal molecules to produce an image
Implementation Method 3
By refracting and transmitting incident light from a backlight assembly below an LCD panel
Implementation Method 4
The liquid crystal molecules are aligned along the direction of an electric field generated between electrodes formed on the two respective substrates
Data Source
AI summary
A liquid crystal display device includes a liquid crystal panel; a mth gate line, a (m+1)th gate line, a (m+2)th gate line and a (m+3)th gate line in the liquid crystal panel, wherein m is a natural number; at least one data line crossing the mth gate line, the (m+1)th gate line, the (m+2)th gate line and the (m+3)th gate line; a timing controller generating a data signal, a control signal, a first flicker signal and a second flicker signal; a gate driver generating a mth gate signal and a (m+2)th gate signal using the first flicker signal and generating a (m+1)th gate signal and a (m+3)th gate signal using the second flicker signal, the mth gate signal and the (m+2)th gate signal being supplied to the mth gate line and the (m+2)th gate line, respectively, the (m+1)th gate signal and the (m+3)th gate signal being supplied to the (m+1)th gate line and the (m+3)th gate line, respectively.