LCD Gate Driver Pre-Charging to Reduce RC Delay
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Solution Overview
Problem
As liquid crystal display (LCD) panels increase in size, resistance-capacitance (RC) time delays in data and gate lines lead to signal delays, affecting charging rates and display quality due to increased RC time delay, especially at display areas farther from the gate driving part, resulting in decreased display quality.
Innovation Solution
A display apparatus comprising a display panel, memory, bit-data convertor, switch, and gate driver, where the bit-data convertor determines k-bit data based on image data changes and outputs total count bit data, and the switch generates pulse control signals with adjusted pre-charging periods to reduce RC time delays, improving signal transmission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the LCD panel size is increased, then the display area is enlarged, but the RC time delay increases causing signal delays and decreased display quality
Solution Approach 1:
The patent applies preliminary action by performing a pre-charging period before the main charging period. During the pre-charging period, the gate signal is maintained at a first voltage level to preliminarily charge the pixel electrodes, ensuring that even distant pixels receive sufficient charge before the main data charging phase. This preliminary charging action compensates for the RC time delay in larger panels, allowing the display area to be enlarged without sacrificing signal timing quality.
2Area of stationary object
If the display area is increased, then the panel size is enlarged, but the charging rate of pixels decreases due to RC time delay
Solution Approach 1:
The gate driver performs a pre-charging action by maintaining the gate signal at a first voltage level during a pre-charging period before the main charging period. This preliminary action ensures that pixels, especially those farther from the gate driving part, receive initial charge that compensates for RC time delay effects, thereby maintaining adequate charging rates across the entire enlarged display area.
Solution Approach 2:
The patent applies dynamics by making the gate signal voltage level and charging period adjustable. The gate driver can dynamically switch between a first voltage level during the pre-charging period and a second voltage level during the main charging period. This dynamic adjustment of voltage levels and timing allows the charging rate to be optimized for different display areas and RC delay conditions, maintaining productivity as the panel size increases.
3Device complexity
If a fixed gate signal charging period is used, then the circuit is simple, but display quality deteriorates at display areas farther from the gate driving part
Solution Approach 1:
The patent applies segmentation by dividing the charging period into two distinct segments: a pre-charging period and a main charging period. During the pre-charging period, the gate signal operates at a first voltage level, and during the main charging period, it switches to a second voltage level. This segmentation allows different charging strategies to be applied to different temporal phases, ensuring uniform display quality across the entire panel while maintaining relatively simple circuit implementation through systematic timing control.
Data Source
AI summary
A display apparatus includes a display panel, a memory, a bit-data convertor, a switch, and a gate driver. The display panel includes pixels. Each pixel is connected to one of the data lines and one of the gate lines. The memory stores a plurality of image data corresponding to a frame period. The bit-data convertor determines a plurality of bit data. Each of the bit data corresponds to a degree of change between adjacent image data among the plurality of image data, obtains a sum of the bit data, and outputs the sum of the bit data as a total count bit data value. The switch outputs a first pulse control signal corresponding to the total count bit data value. The gate driver generates a gate signal based on the first pulse control signal, and to output the gate signal to one of the gate lines.