LCD Gate Driver Shift Registers for Non-Overlapping Gate Pulses
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Solution Overview
Problem
Liquid crystal display (LCD) panels using a multi-switch architecture face challenges in generating precise gate-line signals with non-overlapping front and rear pulses to effectively select and control sub-pixel segments, which is crucial for minimizing color washout and improving visual effects.
Innovation Solution
A gate driver circuit comprising a series of shift registers and a timing control module generates gate-line signals with specific pulse lengths and timing relationships between front and rear pulses, utilizing pull-up and pull-down circuits with switching elements and capacitors to produce non-overlapping pulses, ensuring accurate signal generation for each gate line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If a multi-switch architecture is used to control sub-pixel segments, then the visual effect and color accuracy are improved, but the complexity of generating precise non-overlapping gate-line signals increases
Solution Approach 1:
The gate driver circuit is segmented into multiple independent shift registers, with each shift register responsible for generating control signals for specific gate lines. This segmentation allows each register to independently manage the complex timing requirements for front and rear pulses, thereby improving visual effect while distributing the signal generation complexity across multiple modular units rather than concentrating it in a single complex circuit.
2Manufacturing precision
If front pulse and rear pulse are generated with precise timing to avoid overlap, then sub-pixel segment selection accuracy is improved, but the device complexity increases
Solution Approach 1:
The shift registers are configured to preliminarily establish the timing relationships between front and rear pulses through their inherent clock signal sequencing. By pre-configuring the clock phases and using the natural propagation delay through the shift register stages, the circuit ensures non-overlapping pulses are generated automatically, improving timing precision while avoiding the need for additional complex timing control circuitry.
Solution Approach 2:
Clock signals serve as intermediaries between the control logic and the pulse generation process. The shift registers use multiple clock phases (CLK0, CLK1, CLK2, CLK3) as mediators to coordinate the generation of front and rear pulses, ensuring precise timing and non-overlapping operation without requiring direct complex interaction between the pulse generation stages themselves.
3Object-affected harmful factors
If gate line signals with specific pulse lengths are generated to control sub-pixel segments, then the color washout is reduced, but the signal generation complexity increases
Solution Approach 1:
The gate driver employs periodic clock signals with specific phases to generate front and rear pulses with predetermined lengths. By using periodic clocking sequences (CLK0-CLK3) that repeat at fixed intervals, the circuit automatically produces the required pulse durations for effective sub-pixel control, reducing color washout while maintaining manageable complexity through the regularity of the periodic operation.
Data Source
AI summary
A gate driver for use in a liquid crystal display has a plurality of shift registers connected in series. Each of the shift registers is used to provide a gate-line pulse to a row of pixels in the liquid crystal display. The gate-line pulse has a front pulse and a rear pulse and the shift register has a front-pulse generating part and a rear-pulse generating part for generating to corresponding pulse. Each of the pulse generating parts has a first pull-up circuit to generate a voltage level to keep a switching element in a second pull-up circuit conducting so as to generate a front or rear pulse, in response to a corresponding clock signal, and two pull-down circuits, in response to the voltage level, to allow the front or rear pulse to be generated only at a pull-down period.