LCD Gate Driver Timing to Prevent First-Row Brightness Defects
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Solution Overview
Problem
In liquid crystal displays, the first gate signal is distorted due to a high start signal period longer than the horizontal scanning period, leading to malfunction and uneven pixel brightness, where the first pixel row appears brighter than others.
Innovation Solution
The gate driver outputs gate signals with a first clock signal having a longer high period and a second clock signal with an opposite phase, ensuring the first gate signal is discharged before data signals are applied, and includes a dummy stage to prevent distortion, with specific transistor configurations to enhance discharge capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a start signal with a high period longer than the horizontal scanning period is applied to the first stage, then the gate driver can be simplified in structure, but the first gate signal becomes distorted and pixels in the first pixel row display abnormally (brighter than other pixels)
Solution Approach 1:
The gate driver is segmented into a first gate driver and a second gate driver. The first gate driver generates the first gate signal in response to a first clock signal, while the second gate driver generates the second gate signal in response to a second clock signal. This segmentation allows independent control of the clock signals to prevent distortion in the first gate signal while maintaining overall system simplicity.
Solution Approach 2:
The patent applies different clock signals (first clock signal and second clock signal) to the first and second gate drivers respectively. The first clock signal has a high period longer than the horizontal scanning period, while the second clock signal has a high period equal to or shorter than the horizontal scanning period. This dynamic differentiation resolves the contradiction by allowing the first gate driver to operate with a simplified long-period clock while the second gate driver ensures proper timing for the remaining gate signals.
2Device complexity
If the first gate signal is not fully discharged before the second data signal is applied, then the circuit operation can be simplified, but pixel voltage is reduced and pixels in the first pixel row appear brighter than other pixels
Solution Approach 1:
The patent uses different clock signal periods to dynamically control the discharge timing of gate signals. The second clock signal has a high period equal to or shorter than the horizontal scanning period, ensuring that the first gate signal is fully discharged before the second data signal is applied to the data line. This dynamic timing control maintains simple circuit operation while ensuring uniform pixel brightness across all pixel rows.
Data Source
AI summary
A display apparatus includes a gate driver which sequentially outputs a gate signal at a high state in response to a gate control signal and a data driver which converts image data into a data signal in response to a data control signal. The display apparatus further includes a display panel which includes a plurality of gate lines which sequentially receive the gate signal, a plurality of data lines which receive the data signal and a plurality of pixels connected to the gate and data lines and which receive the data signal in response to the gate signal to display an image. The polarity of the data signal is inverted after the gate signal transitions to a low state.