LCD Gate Driver Timing Control for Slim-Bezel Stereoscopic Displays
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Solution Overview
Problem
Existing liquid crystal displays face challenges in controlling gate-on timing and discharging timing effectively, which affects display quality and bezel width, particularly in achieving slim bezel designs and stereoscopic image display.
Innovation Solution
A gate driver IC chip that receives multiple scanning start signals and clock control signals, generating independent timing for gate-on voltages applied to gate lines and charge sharing lines, allowing for synchronized and overlapping gate-on voltages to improve charging time and display quality, while enabling a slim bezel width of less than 10 mm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional gate driver with single scanning start signal is used, then the device complexity is low, but the gate-on timing control precision and discharging timing control precision are insufficient
Solution Approach 1:
The gate driver is divided into multiple independent shift registers (first shift register, second shift register, third shift register, fourth shift register), each handling different gate lines and controlled by independent scanning start signals. This segmentation allows precise control of gate-on timing for different regions while maintaining modular circuit complexity
Solution Approach 2:
The gate driver dynamically selects which shift register to activate based on the received scanning start signal. When a scanning start signal is received, the corresponding shift register is activated to output gate-on voltages to specific gate lines, enabling dynamic timing control without permanently complex circuit paths
2Manufacturing precision
If charging time is increased to improve display quality, then the display quality improves, but the bezel width increases
Solution Approach 1:
While one shift register is outputting gate-on voltages to gate lines, other shift registers simultaneously output gate-on voltages to charge sharing lines. This continuous parallel operation ensures charging action is maintained without interruption, achieving sufficient charging time within the display area without requiring larger bezel space
Solution Approach 2:
The patent introduces temporal dimension to the charging process by enabling overlapping gate-on voltages from multiple shift registers at different times. This allows the charging operation to extend into the time domain rather than requiring additional spatial area, thus maintaining slim bezel width while ensuring adequate charging time
3Measurement precision
If multiple scanning start signals are used to control different gate lines, then the gate-on timing control precision improves, but the device complexity increases
Solution Approach 1:
Each shift register is designed to be multi-functional, capable of serving both as a gate line driver and a charge sharing line driver depending on which scanning start signal is active. This universality reduces the need for separate dedicated circuits for each function, balancing control precision with circuit complexity
Data Source
AI summary
A gate driver includes a gate integrated circuit (“IC”) chip which receives at least two scanning start signals and at least four clock control signals, and outputs a plurality of gate-on voltages, where at least two clock control signals of the at least four clock control signals are generated based on one scanning start signal of the at least two scanning start signals, timings of the at least two scanning start signals are independent of each other, and timings of the at least two clock control signals based on the one scanning start signal are independent of each other.