LCD Gate Driving Circuit With Leakage Blocking Stages
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Solution Overview
Problem
Existing gate driving circuits for liquid crystal display (LCD) apparatuses face challenges in maintaining an operating margin due to changes in transistor threshold voltage and suffer from increased leakage current, which affects the reliability and efficiency of the display.
Innovation Solution
A gate driving circuit with multiple stages that utilize input units to determine voltage levels, driving units to output carry and gate signals based on specific clock signals, and leakage blocking units to prevent transistor leakage, ensuring stable voltage levels and reduced leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate driving circuits are used, then the circuit structure is simple, but the operating margin is reduced due to threshold voltage changes and leakage current increases
Solution Approach 1:
The gate driving circuit is divided into multiple stages, where each stage includes an input unit, first driving unit, second driving unit, and leakage blocking unit. This segmentation allows each unit to perform a specific function independently, improving the overall operating margin while managing complexity through modular design.
Solution Approach 2:
A leakage blocking unit is introduced as an intermediary component between the driving units and the output. This unit specifically blocks leakage current, which is the harmful factor reducing operating margin, without requiring complete redesign of the entire circuit structure.
2Reliability
If conventional driving units are used, then the circuit complexity is low, but the leakage current of transistors increases
Solution Approach 1:
The leakage blocking unit is designed to specifically target and block leakage current paths. By identifying where leakage occurs (in the transistor connections between stages), the circuit converts the harmful leakage current into a controlled parameter that can be blocked, thereby improving gate signal transmission reliability.
3Speed
If simple clock signal timing is used, then the circuit operation is simple, but the falling time of gate signal increases
Solution Approach 1:
The clock signal timing is made dynamic by introducing multiple clock signals (first, second, and third clock signals) with different phases and timing characteristics. The third clock signal specifically has a falling time that precedes the first clock signal, enabling faster gate signal falling time. This dynamic timing approach improves speed while managing complexity through coordinated clock management.
Data Source
AI summary
A gate driving circuit includes a plurality of stages, each stage including an input unit to determine a level of voltage to input to a first node based on the first and second input signals and the first clock signal that is input according to the level of the voltage input to the first node and a first gate-off voltage that is input in response to the second clock signal, a second driving unit outputting the gate signals based on the third clock signal input according to the voltage input to the first node and a second gate-off voltage input in response to the second clock signal, and a leakage blocking unit blocking leakage current of a transistor by maintaining a level of voltage input to a third node connected to the first node via at least one transistor.