Liquid Crystal Panel Gate Line Structure for Reduced Exposure Processes
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Solution Overview
Problem
The manufacturing process of liquid crystal panels is costly due to the high number of exposure processes required, particularly in forming the gate line and pixel electrode, which increases production expenses.
Innovation Solution
Implementing a multiple gradation mask exposure process to form the gate line and pixel electrode in a single exposure step, and using a two-layered structure for the gate line with a higher conductivity material on top of the transparent conductive material, allowing for the formation of connecting conductors and auxiliary common lines without increasing the number of exposure processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple exposure processes are used to form gate line and pixel electrode separately, then manufacturing precision is improved, but manufacturing cost increases and productivity decreases
Solution Approach 1:
The patent combines the formation of gate line and pixel electrode into a single exposure process by using a multi-layer resist structure. The first resist layer is patterned to form the gate line, and the second resist layer is patterned to form the pixel electrode, both in one exposure step. This merging of operations maintains manufacturing precision while significantly improving productivity by reducing the number of exposure processes.
Solution Approach 2:
The patent segments the resist film into multiple layers (first resist layer and second resist layer), each with different functions. The first resist layer serves as a mask for gate line formation, while the second resist layer serves as a mask for pixel electrode formation. This segmentation allows both patterns to be formed simultaneously in one exposure process without compromising precision.
2Manufacturing precision
If multiple exposure processes are used to form gate line and pixel electrode separately, then manufacturing precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent merges multiple exposure operations into a single exposure process by using a multi-layer resist structure with different light transmissivity characteristics. This reduces the consumption of expensive photo masks and exposure time, thereby lowering manufacturing costs while maintaining the precision required for gate line and pixel electrode formation.
Solution Approach 2:
The patent changes the light transmissivity parameter of different resist layers to achieve selective pattern formation. The first resist layer has different light transmissivity than the second resist layer, allowing the exposure light to penetrate differently through each layer and form distinct patterns (gate line and pixel electrode) simultaneously. This parameter change enables cost-effective single-exposure manufacturing.
3Device complexity
If single-layer gate line is used, then device complexity is reduced, but electrical conductivity is insufficient
Solution Approach 1:
The patent uses a composite structure for the gate line consisting of a first conductor layer and a second conductor layer with different material compositions. The first conductor layer provides basic conductivity, while the second conductor layer enhances the electrical conductivity. This composite approach improves reliability without significantly increasing device complexity, as the additional layer is integrated into the existing multi-layer resist structure.
Data Source
AI summary
A gate line (40) has a two-layered structure comprising a lower gate line (40a) made of material identical to a pixel electrode (70), and positioned in the same layer as the pixel electrode (70), and an upper gate line (40b) layered on the lower gate line (40b), and made of material having a higher electrical conductivity than the transparent conductive material. According to this structure, it is possible to reduce the number of times performing exposure processes in manufacturing an in-plane switching type liquid crystal panel.


