LCD Gate Line Layout for Faster Pixel Charging and Release
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Solution Overview
Problem
Existing liquid crystal display (LCD) panels face issues with increased resolution leading to shortened charging times, slower scanning speeds, and uneven discharging times of thin-film transistors, which affect display performance and are not adequately addressed by existing technologies.
Innovation Solution
The display panel incorporates a configuration with parallel first and second gate lines, where first thin film transistors are connected to the first gate lines and second thin film transistors are connected to the second gate lines, with a gate driver positioned on both sides or one side to accelerate the turning off of second transistors, and a balanced connection ratio of first to second transistors to optimize charging and signal release.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If a liquid crystal display is used, then power consumption is reduced compared to CRT, but viewing angle is limited and colors appear unnatural when viewed from oblique angles
Solution Approach 1:
The invention divides the liquid crystal display into multiple independent sub-pixels (red, green, blue) arranged in a specific pattern, with each sub-pixel having its own electrode structure. This segmentation allows independent control of color emission and enables the implementation of different voltage patterns for different viewing angles, thereby maintaining color accuracy while reducing power consumption.
Solution Approach 2:
The patent implements different electrode configurations and voltage control strategies for different regions of the display. Specifically, the first and second electrodes are positioned at different locations relative to the liquid crystal layer, allowing localized electric field control that compensates for viewing angle-dependent color shifts while optimizing power consumption in different display zones.
2Device complexity
If thin film transistor is used to control liquid crystal, then integration is improved, but transistor performance degrades over time due to hot carrier effects
Solution Approach 1:
The invention incorporates a dedicated compensation electrode structure that is pre-configured to counteract hot carrier effects before they significantly degrade transistor performance. The additional electrode allows for preliminary compensation of threshold voltage shifts by applying corrective voltage patterns, thereby maintaining reliable transistor operation over extended periods while preserving the integrated thin film transistor architecture.
3Manufacturing precision
If display resolution is increased to meet HD requirements, then image quality is improved, but power consumption increases
Solution Approach 1:
The patent implements a selective activation strategy where not all sub-pixels are driven at full intensity simultaneously. By using the additional electrode to create localized electric field enhancements, the display can achieve HD resolution with reduced overall power consumption by activating only necessary pixel elements at optimal intensity levels rather than uniformly driving the entire display at maximum resolution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances display performance by improving charging and signal release speeds, reducing production costs, and ensuring consistent transistor control, thereby addressing the limitations of existing LCD technologies.
Implementation Method 1
liquid crystal which changes its molecular arrangement in response to an electric field to thereby change the polarization of light passing through it
Implementation Method 2
first and second electrodes are positioned at different locations relative to the liquid crystal layer and are used to generate an electric field across the liquid crystal layer
Data Source
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AI summary
A display panel and a display device. The display panel comprises an array substrate. A plurality of data lines (D1, ..., Dh), a plurality of gate line groups (G1, ..., Gn) arranged in parallel, and a plurality of first thin film transistors (T1) are provided on the array substrate. Each of the gate line groups (G1, ..., Gn) comprises a first gate line (g1, ..., gn) and a second gate line (g1', ..., gn'). Gates of the first thin film transistors (T1) are connected to corresponding first gate lines (g1, ..., gn), sources of the first thin film transistors (T1) are connected to corresponding second gate lines (g1', ..., gn'), and drains of the first thin film transistors (T1) are connected to a first common electrode (COM1).