Gate Scanning Line Impedance Reduction in LCD Array Substrates
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Solution Overview
Problem
The high impedance of gate scanning metal wires in liquid crystal display (LCD) panels leads to increased driving power consumption and reduced pixel charge/discharge speed due to the narrow width of gate scan lines required for maintaining aperture ratio.
Innovation Solution
The gate scanning lines are electrically connected to a light-shielding conductive layer through through holes in the buffer and insulating layers, allowing for reduced impedance and unchanged width of gate scanning lines, thereby reducing power consumption and enhancing pixel charging/discharging speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the width of gate scan lines is reduced to maintain aperture ratio, then the aperture ratio of the display panel is maintained, but the impedance of the gate scanning metal wire increases and driving power consumption increases
Solution Approach 1:
The gate scanning line and light-shielding conductive layer are electrically connected through through-holes, merging their functions. The light-shielding layer serves dual purposes: blocking light and providing additional conductive path, thereby reducing impedance without increasing the visible gate line width, maintaining aperture ratio while reducing power consumption
Solution Approach 2:
The solution transitions from a two-dimensional planar connection to a three-dimensional structure by introducing through-holes that penetrate multiple layers (buffer layer and first insulating layer). This vertical dimensionality allows electrical connection between gate scanning lines and light-shielding conductive layer without occupying additional horizontal space, thus maintaining aperture ratio while reducing impedance
2Area of stationary object
If the width of gate scan lines is reduced to maintain aperture ratio, then the aperture ratio of the display panel is maintained, but the pixel charge and discharge response speed decreases
Solution Approach 1:
By merging the gate scanning line with the light-shielding conductive layer through electrical connection via through-holes, the effective conductive cross-section is increased. This reduces impedance and accelerates charge and discharge response speed without compromising aperture ratio
Solution Approach 2:
The through-hole connection structure utilizes the vertical dimension to establish electrical pathways through the buffer and insulating layers, enabling faster signal transmission without expanding the horizontal footprint of the gate scanning line, thus improving response speed while maintaining aperture ratio
Data Source
AI summary
An array substrate, a manufacturing method thereof, and display panel are provided. Gate scanning lines and Light-shielding conductive layer are electrically connected, so that a width of the gate scanning line is substantially unchanged from the conventional technology to ensure an aperture ratio of a display panel. Therefore, an impedance of the wire used to transmit the scanning electrical signal is reduced, so that the display panel driving power consumption is reduced to increase the corresponding speed of pixel charging and discharging.