LCD Pixel Circuit with HSD3 Driving for Voltage Uniformity
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Solution Overview
Problem
Conventional liquid crystal display (LCD) devices face challenges in reducing power consumption while maintaining image quality, as high voltage application can lead to irreversible degradation and the mura effect due to non-uniform potential voltages across sub-pixels, especially in thin film transistor (TFT) LCDs.
Innovation Solution
The implementation of an HSD3 driving scheme with a specific pixel configuration and waveform for gate signals, including multiple transistors and data signal inversion, to ensure uniform voltage distribution across sub-pixels, reducing power consumption and improving charging and holding performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If high voltage is applied to liquid crystal layer for long period, then display performance is improved, but liquid crystal molecules deteriorate irreversibly
Solution Approach 1:
The patent implements frame inversion and row inversion schemes where the polarity of voltages applied across liquid crystal cells is alternated periodically. During even frames, positive voltage is applied to even rows and negative voltage to odd rows, while during odd frames, the polarity is reversed. This periodic polarity switching prevents liquid crystal molecule deterioration while maintaining display performance.
2Reliability
If polarity inversion schemes are used frequently, then liquid crystal degradation is prevented, but power consumption increases
Solution Approach 1:
The patent introduces a pre-charge period before the switching period where storage capacitors are charged to the required voltage levels. This preliminary charging action ensures that when polarity inversion occurs, the capacitors are already prepared, reducing the energy required during the actual switching operation and minimizing power consumption while maintaining liquid crystal stability.
3Use of energy by moving object
If HSD2 driving scheme is used, then power consumption is reduced, but mura effect occurs due to non-uniform potential voltages
Solution Approach 1:
The patent applies different gate signal waveforms to different sub-pixels within the same pixel. The first sub-pixel receives a gate signal with a first waveform while the second sub-pixel receives a gate signal with a second waveform. This local differentiation ensures that each sub-pixel receives the appropriate voltage to achieve uniform potential distribution, eliminating the mura effect while maintaining the power consumption benefits of the HSD2 scheme.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The HSD3 driving scheme achieves reduced power consumption, improved uniformity in pixel voltage, and enhanced display quality by minimizing the mura effect and maintaining image integrity over time.
Implementation Method 1
charge the corresponding liquid crystal capacitor and storage capacitor of the pixel row for aligning orientations of the corresponding liquid crystal cells associated with the pixel row to control light transmittance therethrough
Data Source
AI summary
A liquid crystal display (LCD) and methods of driving same. In one embodiment, the LCD) includes a plurality of gate lines, {Gn}, spatially arranged along a row direction; a plurality of data lines, {Dm}, spatially arranged along a column direction perpendicular to the row direction, and a plurality of pixels, {Pn,m}, spatially arranged in the form of a matrix, where m=1, 2, . . . , M, n=1, 2, . . . , N, and M and N are positive integers. Each pixel Pn,m is defined between two neighboring gate lines Gn and Gn+1 and two neighboring data lines Dm and Dm+1, and comprises a first sub-pixel electrode, a second sub-pixel electrode, a first transistor having a gate electrically coupled to the gate line Gn+1, a source and a drain electrically coupled to the first sub-pixel electrode, a second transistor having a gate electrically coupled to the gate line Gn, a source electrically coupled to the source of the first transistor and a drain electrically coupled to the second sub-pixel electrode, and a third transistor having a gate electrically coupled to the gate line Gn+2, a source electrically coupled to one of the two neighboring data lines Dm and Dm+1 and a drain electrically coupled to the sources of the first and second transistors.