Liquid Crystal Display Ion Stain Prevention via Polarity Inversion
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Solution Overview
Problem
Active matrix liquid crystal displays suffer from staining issues due to ion polarization and accumulation, which are exacerbated by long-term application of DC voltage, leading to degraded alignment characteristics and non-uniform stains across panels.
Innovation Solution
A liquid crystal display system that periodically inverts the polarity of data voltage supplied to data lines and synchronizes gate pulses with alternating polarities, using a timing controller to generate pre-gate and real gate start pulses during specific periods, effectively changing the movement vectors of ions in the liquid crystal layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DC voltage is applied to liquid crystal layer for long time, then liquid crystal display can maintain stable operation, but ions accumulate and polarize causing stains and degraded alignment characteristics
Solution Approach 1:
The patent applies periodic action by alternating the polarity of data voltage between positive and negative every frame period. This periodic polarity reversal prevents ion accumulation and polarization by continuously changing the electric field direction, thereby eliminating stains while maintaining stable display operation.
2Object-affected harmful factors
If data voltage polarity is inverted every frame period, then ion accumulation is prevented, but gate driver circuit complexity increases due to need for pre-gate and real gate start pulses
Solution Approach 1:
The patent applies preliminary action by generating a pre-gate start pulse before the actual gate pulse to prepare the gate driver circuit for polarity inversion. The pre-gate start pulse is generated during the blanking period and triggers the gate driver to output the appropriate polarity of data voltage, enabling smooth transition and reducing circuit complexity.
Solution Approach 2:
The timing controller acts as an intermediary by generating both pre-gate start pulse and real gate start pulse to coordinate between data driver and gate driver. This intermediary mechanism simplifies the overall circuit design by centralizing the pulse generation and coordination functions.
3Reliability
If pre-gate start pulse is generated during blank period, then alignment characteristics are maintained, but display quality may be affected due to dummy data processing
Solution Approach 1:
The patent applies local quality by processing only the necessary portion of the display area during the blanking period. The pre-gate start pulse is generated and applied locally to maintain alignment characteristics without affecting the entire display area, thereby preserving display quality while ensuring proper alignment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents the accumulation of ions based on polarity, reducing the occurrence and severity of stains, thereby maintaining alignment characteristics and display quality over time.
Implementation Method 1
If a DC voltage is applied to a liquid crystal layer of the liquid crystal display for a long time, negative ions move in the same vector direction and positive ions move in a vector direction opposite the vector direction of the negative ions based upon a polarity of an electric field applied to liquid crystals. Hence, the ions in the liquid crystal layer are polarized.
Data Source
AI summary
A liquid crystal display and a method of driving the same are disclosed. The liquid crystal display includes a data drive circuit that supplies a data voltage, whose a polarity is periodically inverted, to the data lines, a gate drive circuit, and a timing controller. The gate drive circuit sequentially supplies a first gate pulse synchronized with a first data voltage to gate lines, and sequentially supplies a second gate pulse synchronized with a second data voltage having a polarity opposite a polarity of the first data voltage, to the gate lines. The timing controller generates a pre-gate start pulse for controlling an output of the first gate pulse during a blank period, and then generates a real gate start pulse for controlling an output of the second gate pulse during an initial period of a frame period following the blank period.