Liquid Crystal Display Lead-Out Lines Parasitic Capacitance
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Solution Overview
Problem
The challenge in liquid crystal display devices is to reduce the wiring width and space of lead-out lines while minimizing the effects of parasitic capacitance, which causes waveform rounding and deteriorates display quality, especially when implementing a multilayer structure at the source-line side.
Innovation Solution
The implementation of a liquid crystal display device with lead-out lines that include a tilt portion wired parallel to the peripheral direction, where the tilt portions of overlapping lead-out lines have a smaller applied voltage difference, allowing for a multilayer structure without significant parasitic capacitance effects, and the use of a short circuit to adjust voltage phases and reduce power requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a multilayer structure of lead-out lines is implemented to decrease wiring width and space, then the number of lead-out lines increases and peripheral region size is reduced, but parasitic capacitance between overlapped lines causes waveform rounding
Solution Approach 1:
The patent applies equipotentiality by configuring overlapping lead-out lines to have the same voltage phase, creating an equipotential relationship between adjacent lines in the multilayer structure. This is achieved by controlling the voltage application timing and phase for each lead-out line layer, ensuring that lines occupying the same spatial position across different layers maintain equal potential, thereby eliminating potential difference and the associated parasitic capacitance effects that would otherwise cause waveform rounding.
Solution Approach 2:
The patent changes the voltage phase parameter of lead-out lines to resolve the parasitic capacitance issue. By adjusting the phase relationship between voltages applied to different lead-out line layers, the patent transforms the harmful capacitance coupling into a non-harmful configuration. Specifically, lines in overlapping positions are assigned voltages with the same phase, changing the electrical parameter relationship to eliminate the adverse effects while maintaining the compact multilayer wiring structure.
2Volume of stationary object
If wiring width and wiring space of lead-out lines are decreased to reduce IC chip size, then component count is reduced, but manufacturing yield deteriorates due to fabrication limits
Solution Approach 1:
The patent transitions from a single-layer planar wiring layout to a multilayer three-dimensional wiring structure. By utilizing multiple layers stacked vertically, the patent increases the effective wiring capacity without increasing the planar footprint. This dimensional change allows more lead-out lines to be accommodated within the same IC chip area, effectively reducing chip size while maintaining adequate wiring dimensions that satisfy manufacturing precision requirements.
3Measurement precision
If the number of gate lines and source lines is increased to increase resolution, then display quality improves, but the number of necessary components increases
Solution Approach 1:
The patent employs a multilayer wiring structure to increase the number of lead-out lines without proportionally increasing the number of external components. By stacking multiple wiring layers, the patent effectively multiplies the wiring capacity within the same physical footprint, allowing high-resolution displays to be achieved while keeping the IC chip and peripheral component count manageable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration suppresses the effects of parasitic capacitance, preventing waveform rounding and reducing power consumption, thereby enhancing display quality and contrast.
Implementation Method 1
an effect caused by parasitic capacitance formed between the lead-out lines overlapped with each other in a plan view becomes a problem. Specifically, capacitance coupling through an insulating layer occurs between the lead-out lines
Data Source
AI summary
A liquid crystal display device includes a display region, a plurality of lead-out lines led from the display region, and an application circuit that applies a voltage to liquid crystal in the display region through each of the lead-out lines. Each of the lead-out lines has a tilt portion wired with a directional component parallel to a peripheral direction enclosing the display region in a plan view, and when a difference between a voltage applied to one of the lead-out lines and a voltage applied to another one of the lead-out lines is specified as an applied voltage difference, each of the lead-out lines is wired such that, in a plan view, the taper portion of one of the lead-out lines is overlapped with the taper portion of another one of the lead-out lines having the applied voltage difference lower than a difference with adjacent one of the lead-out lines.