LCD Level Shifter Single Voltage Signal Pin Reduction
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Solution Overview
Problem
The complexity and cost of the timing controller in LCD devices are increased due to the need for multiple pins and a complicated circuit structure to generate and transmit multiple gate shift clock signals, as well as the stress on pull-down transistors in the gate driver, which complicates the arrangement of elements on a PCB.
Innovation Solution
The LCD device uses a timing controller that generates a single voltage signal for alternately driving two transistors, with a level shifter that generates two switching signals using this voltage signal, reducing the number of pins and simplifying the circuit structure by using a switching signal generating unit with a flip-flop, delay circuits, and AND gates to produce VDD_EVEN and VDD_ODD signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple gate shift clock signals are generated and transmitted from the timing controller, then the gate driver can be driven properly, but the number of pins in the timing controller increases
Solution Approach 1:
The patent combines multiple gate shift clock signals into a single voltage signal by merging their functions. The level shifter generates multiple clock signals (GSC1-GSC4) from one voltage signal (VDD_EO), allowing the timing controller to use fewer pins while still providing all necessary clock signals to the gate driver.
Solution Approach 2:
The patent introduces a level shifter as an intermediary component between the timing controller and gate driver. This intermediary generates multiple gate shift clock signals from a single voltage signal, enabling the timing controller to reduce its pin count while ensuring proper gate driver operation through the mediating level shifter.
2Reliability
If multiple gate shift clock signals are transmitted via level shifter, then the gate driver receives proper signals, but the number of input pins in the level shifter increases
Solution Approach 1:
The patent segments the level shifter's function into two parts: receiving a single voltage signal from the timing controller, and internally generating multiple gate shift clock signals. This segmentation allows the level shifter to have only one input pin from the timing controller while still providing multiple clock signals to the gate driver through its internal circuitry.
Solution Approach 2:
The level shifter merges multiple clock signal generation functions into a single component that receives one voltage signal. By combining the generation of GSC1-GSC4 clocks within the level shifter, the patent reduces the number of input pins required from the timing controller while maintaining proper signal transmission.
3Reliability
If two pull-down transistors are used alternately in the gate driver, then the transistor stress is reduced, but the circuit structure becomes complicated
Solution Approach 1:
The patent implements periodic action by alternately switching between two pull-down transistors (PD1 and PD2) in the gate driver. The switching signals VDD_EVEN and VDD_ODD control the transistors to operate in alternating periods, allowing each transistor to rest during the other's active period, thereby reducing overall transistor stress while maintaining the discharging function.
Solution Approach 2:
The patent applies the discarding and recovering principle by having two pull-down transistors take turns being active and inactive. When one transistor is active and experiencing stress, the other is recovered and resting. This alternating usage pattern distributes the stress over time and allows transistors to recover during their inactive periods, improving reliability.
Data Source
AI summary
An LCD device is discussed in which a level shifter generates two switching signals, and transmits the generated signals to a gate driver of a liquid crystal display panel by the use of one voltage signal transmitted from a timing controller. The LCD device according to an embodiment includes a liquid crystal display panel in which a gate driver for alternately driving two transistors is formed; a data driver which drives data lines of the liquid crystal display panel; a timing controller which generates one voltage signal for switching the two transistors, and outputs the one voltage signal; and a level shifter which generates two of first and second switching signals to switch the two transistors by using the one voltage signal, and outputs the generated switching signals to the gate driver.