LCD Level Shifter Stepwise Voltage Modulation
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Solution Overview
Problem
Liquid crystal displays (LCDs) suffer from flickering and image sticking due to kickback voltage caused by parasitic capacitance, which affects the voltage applied to pixel electrodes, leading to suboptimal display quality.
Innovation Solution
A liquid crystal display system that includes a clock generator and level shifter to produce clock signals with stepwise decreasing voltages, which are used to modulate gate pulses, reducing the voltage difference between gate-high and gate-low voltages and thereby compensating for kickback voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate driving circuit is used, then the circuit structure is simple, but kickback voltage causes flickering and image sticking
Solution Approach 1:
The gate pulse voltage is segmented into multiple levels (gate high voltage, modulation voltage, gate low voltage) through the level shifter. The clock signals are divided into different voltage levels that sequentially control the gate pulse, allowing kickback voltage compensation without requiring a completely complex circuit architecture.
Solution Approach 2:
The gate pulse voltage is made dynamic through sequential modulation. The level shifter dynamically adjusts the gate pulse voltage levels based on sequential clock signals, enabling the circuit to adaptively compensate for kickback voltage while maintaining a relatively simple overall structure.
2Reliability
If gate pulses are modulated with multiple clocks, then kickback voltage is compensated, but the number of clocks increases
Solution Approach 1:
The level shifter uses periodic clock signals with different voltage levels to sequentially modulate the gate pulse. By using periodic clocking with three distinct voltage levels (gate high, modulation, gate low), the circuit achieves kickback compensation efficiently without requiring excessive clock signals.
Solution Approach 2:
The clock signals undergo parameter changes in terms of voltage levels. The level shifter generates clock signals at different voltage levels (gate high voltage, modulation voltage lower than gate high, gate low voltage lower than modulation) to modulate the gate pulse, enabling compact representation of multiple voltage states.
3Power
If the voltage difference between gate-high and gate-low is large, then the gate pulse has strong driving capability, but kickback voltage increases
Solution Approach 1:
The level shifter applies preliminary anti-action by introducing a modulation voltage level between gate high and gate low voltages. This intermediate voltage level preemptively counteracts the kickback voltage effect, allowing the gate pulse to maintain strong driving capability while reducing the harmful kickback voltage through sequential voltage modulation.
Solution Approach 2:
The modulation voltage acts as an intermediary between gate high voltage and gate low voltage. The level shifter uses this intermediate voltage level to mediate the transition, enabling the gate pulse to achieve both strong driving capability and reduced kickback voltage through sequential voltage levels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces flickering and image sticking by modulating gate pulses with minimum clocks, improving display quality and simplifying the gate driving circuit configuration.
Implementation Method 1
a level shifter shifting the first and second input clock signals and generating clock signals whose voltages decrease stepwise from a gate high voltage, to a modulation voltage that is lower than the gate high voltage, to a gate low voltage that is lower than the modulation voltage
Implementation Method 2
TFTs provided at intersections of the data lines and the gate lines
Data Source
AI summary
A liquid crystal display is disclosed. The liquid crystal display includes a clock generator generating a first input clock signal and then a second input clock signal; a level shifter shifting the first and second input clock signals and generating clock signals whose voltages decrease stepwise from a gate high voltage, to a modulation voltage that is lower than the gate high voltage, to a gate low voltage that is lower than the modulation voltage; and a liquid crystal panel that includes data lines, gate lines intersecting the data lines, TFTs provided at intersections of the data lines and the gate lines, and a gate shift register sequentially supplying a gate pulse to the gate lines in response to the clock signals input from the level shifter.