Liquid Crystal Display Panel Multi-Layer Source Line Wiring
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Solution Overview
Problem
The increase in the number of source lines between adjacent columns of pixel units in liquid crystal display panels decreases the aperture ratio, affecting the display effect, as existing solutions require a wider wiring area and complex manufacturing processes.
Innovation Solution
The use of source lines on different wiring layers, with line segments disposed orthogonally to the planar direction, reduces the wiring area required and improves the aperture ratio by allowing for more flexible and compact arrangements, such as juxtaposed, overlapping, or staggered configurations, while maintaining electrical connectivity through contact holes and plugs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two source lines are disposed in the same wiring layer between two adjacent columns of pixel units, then the wiring layout is simple, but the wiring area increases and the aperture ratio decreases
Solution Approach 1:
The patent applies dimensionality change by transitioning from a two-dimensional planar wiring layout to a three-dimensional multi-layer wiring structure. Specifically, the first source line is disposed on a first wiring layer while the second source line is disposed on a second wiring layer, allowing both source lines to be positioned between the same two adjacent columns of pixel units without increasing the planar wiring area. This vertical stacking approach resolves the contradiction by maintaining compact lateral dimensions while accommodating multiple source lines through the third dimension.
2Area of stationary object
If the distance between two source lines is shortened to maintain insulation, then the wiring area is reduced, but the manufacturing process complexity increases
Solution Approach 1:
The patent resolves the insulation challenge by utilizing the vertical dimension between wiring layers. Instead of relying solely on lateral spacing or complex planar insulation structures, the first and second source lines are separated by disposing them on different wiring layers (first wiring layer and second wiring layer respectively). This vertical separation provides inherent insulation while allowing the source lines to be positioned close together in the planar direction, thereby reducing the overall wiring area without compromising insulation requirements.
3Adaptability or versatility
If the number of source lines is increased to enable different voltage signals to be written to two rows of pixel units simultaneously, then the voltage writing capability is improved, but the space required for source lines increases and aperture ratio decreases
Solution Approach 1:
The patent enables enhanced voltage writing capability by introducing a multi-layer wiring structure. The first source line on the first wiring layer and the second source line on the second wiring layer can independently provide different voltage signals to two different rows of pixel units simultaneously. This vertical stacking approach allows the display panel to drive more pixel rows without increasing the lateral wiring area, thereby maintaining a high aperture ratio while improving voltage writing versatility.
Solution Approach 2:
The patent applies the nesting principle by placing the second source line on the second wiring layer directly above or adjacent to the first source line on the first wiring layer. This nested arrangement allows both source lines to occupy the same lateral space between two adjacent columns of pixel units, effectively nesting one wiring structure within the vertical space of another, thereby maximizing space utilization and maintaining high aperture ratio.
Data Source
AI summary
A liquid crystal display panel, comprising: a plurality of source lines extending in a first direction, and including a first source line and a second source line; a plurality of gate lines extending in a second direction different from the first direction, and crossing the plurality of source lines; and a plurality of pixel units defined by the plurality of source lines and the plurality of gate lines, in which a plurality of transistors and a plurality of pixel electrode are disposed, respectively; the first source line and the second source line are respectively connected to two adjacent rows of the pixel unit; wherein the first source line comprises a first line segment disposed on a first wiring layer; the second source line comprises a second line segment, and the second line segment is disposed on a second wiring layer different from the first wiring layer.