LCD Output Enable Signal Circuit Timing Adjustment
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Solution Overview
Problem
LCD gate drivers malfunction due to a coupling phenomenon caused by noise in the gate clock signal, especially in LCDs without a gate driver PCB, leading to improper detection of the gate clock signal.
Innovation Solution
A signal generating circuit that receives a gate clock signal and an output enable signal, adjusting the latter to overlap with the rising edge of the gate clock delay signal, ensuring proper operation of the gate driver by synchronizing the signals and reducing noise effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the data driver outputs a large positive or negative polarity voltage relative to the common voltage, then the voltage swing capability is improved, but a coupling phenomenon occurs that adversely affects the gate clock signal and may cause gate driver malfunction
Solution Approach 1:
The patent applies preliminary action by adjusting the output enable signal OE in advance so that its falling edge overlaps with the rising edge of the gate clock delay signal CPV_DEL. This timing adjustment is performed before the coupling phenomenon can adversely affect the gate clock signal detection, thereby preventing the harmful effect while maintaining large voltage swing capability
Solution Approach 2:
The patent introduces the output enable signal OE as an intermediary element that mediates between the data driver output and the gate driver operation. By controlling the timing of OE relative to the gate clock delay signal, it acts as a buffer that prevents the coupling phenomenon from directly affecting gate clock signal detection while allowing large voltage swings to occur
2Device complexity
If the LCD lacks a gate driver PCB, then the device complexity is reduced, but the coupling phenomenon becomes more severe causing gate driver malfunction
Solution Approach 1:
The patent implements feedback by using the gate clock delay signal CPV_DEL (which is a delayed version of the gate clock signal) to adjust the output enable signal OE timing. This feedback mechanism allows the system to automatically compensate for coupling effects without adding complex external circuitry like a gate driver PCB, thereby maintaining reliability while keeping device complexity low
Solution Approach 2:
The patent applies parameter changes by adjusting the timing parameter of the output enable signal OE relative to the gate clock signal. By changing the temporal relationship between these signals (specifically making the falling edge of OE overlap with the rising edge of CPV_DEL), the system compensates for the lack of gate driver PCB isolation and prevents coupling-induced malfunctions
Data Source
AI summary
A signal generating circuit for a liquid crystal display (LCD) includes circuitry adapted to receive a gate clock signal and an output enable signal. The gate clock signal is a combination of a gate-on signal and a gate-off signal and the output enable signal is operable to adjust the width of the gate-on signal. The signal generating circuit adjusts the output enable signal such that a falling edge of the output enable signal overlaps a rising edge of the gate clock signal and thereby delays the gate clock signal for a selected amount of time.