Liquid Crystal Display Panel Extra Data Signal Architecture
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Solution Overview
Problem
High-resolution liquid crystal display devices face gray-scale distortion due to insufficient data voltage write time, especially at high frame rates like 120 Hz and resolutions of 8K or 4K, resulting in compromised picture quality.
Innovation Solution
The liquid crystal display panel incorporates a novel architecture with a gate driving signal, data signal, and control signal, where the control signal includes a gate pulse and data voltage, enabling pixel elements and allowing for extended data voltage write time by alternating signal application across rows and columns, enabling efficient data storage in liquid crystal and storage capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high frame rate (120 Hz) and high resolution (8K or 4K) are implemented, then display quality and refresh rate are improved, but data voltage write time becomes insufficient causing gray-scale distortion
Solution Approach 1:
The pixel array is divided into multiple groups, with each group containing pixel elements that share common scan terminals receiving the same gate driving signal. This segmentation allows independent data voltage application to each group through dedicated data terminals, enabling extended write time for data voltage storage without compromising the overall frame rate performance
Solution Approach 2:
Data voltage is applied to the data terminal before the gate driving signal enables the pixel element. This preliminary action ensures that the liquid crystal capacitor and storage capacitor are fully charged with the correct data voltage before the switching transistor activates, preventing gray-scale distortion even at high frame rates
2Manufacturing precision
If data voltage write time is extended to prevent gray-scale distortion, then picture quality is improved, but the time for writing data signal increases affecting frame rate
Solution Approach 1:
By dividing the pixel array into groups with shared scan terminals, the patent enables parallel data voltage application to multiple pixel groups simultaneously. Each group can receive its data voltage through dedicated data terminals while sharing the same gate driving signal timing, effectively extending write time without increasing the overall frame cycle time
Solution Approach 2:
The patent introduces an additional dimension by providing separate data terminals for each pixel group, independent of the shared scan terminals. This allows data voltage to be applied through a different pathway (data terminal) rather than through the scan terminal, enabling extended write time without affecting the gate driving signal timing
Data Source
AI summary
An Liquid crystal display panel is provided. The Liquid crystal display panel includes a plurality of pixel elements arranged as a pixel array. The Liquid crystal display panel receives a plurality of data signals, a plurality of gate driving signals, a plurality of control signals, and an extra data signal. Each of the gate driving signals includes a gate pulse; each of the data signals includes a data voltage; the extra data signal includes a data voltage; and each of the control signals includes a gate pulse and a data voltage.