LCD Panel Via Hole Segmentation for Impedance Reduction
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Solution Overview
Problem
Conventional LCD panels experience increased impedance of the ITO layer due to the overlapping arrangement of deep and shallow holes, leading to abnormal signal transmission.
Innovation Solution
The LCD panel design includes a substrate with a first metal layer, a gate insulating layer, an active layer, a second metal layer, a passivation layer, and a metal connection layer, where the metal connection layer is connected to both metal layers through via holes with a depth difference that is smaller than the sum of the thicknesses of the gate insulating layer, the active layer, and the second metal layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the deep and shallow holes are arranged overlappingly to achieve potential difference between main pixel and sub-pixel, then color shift is improved, but the ITO layer impedance increases and abnormal signal transmission occurs
Solution Approach 1:
The patent divides the via hole structure into two separate holes: a first via hole for connecting the first metal layer and a second via hole for connecting the second metal layer. This segmentation eliminates the overlapping arrangement that caused the ITO layer impedance problem, while still achieving the necessary electrical connections for color shift improvement.
Solution Approach 2:
The patent introduces a metal connection layer as an intermediary component that connects both the first metal layer and the second metal layer through the first and second via holes respectively. This intermediary structure allows for proper electrical connections without requiring the ITO layer to span the deep overlapping holes, thus reducing impedance and preventing abnormal signal transmission.
2Adaptability or versatility
If the deep hole depth is increased to accommodate overlapping hole arrangement, then the ITO layer length increases, but the ITO layer impedance increases
Solution Approach 1:
The patent segments the via hole function into two separate holes with different depths: the first via hole connects the first metal layer with controlled depth, and the second via hole connects the second metal layer. This segmentation allows each via hole to have optimized depth for its specific connection requirement, avoiding the excessive depth that would increase ITO layer impedance.
Solution Approach 2:
The patent changes the depth parameter of the via holes by introducing two different depth values: a first depth for the first via hole and a second depth for the second via hole. This parameter differentiation allows optimization of each via hole depth according to the specific metal layer connection requirements, thereby controlling the ITO layer impedance within acceptable ranges.
Data Source
AI summary
The present application provides a liquid crystal display (LCD) panel and an LCD device. In the LCD panel, a first metal layer and a second metal layer are connected to a metal connection layer through a first via hole and a second via hole, respectively. A difference between a depth of the first via hole and a depth of the second via hole is smaller than a sum of thicknesses of a gate insulating layer, an active layer, and the second metal layer. Accordingly, the depth of the first via hole is reduced, a length of the meal connection layer in the first via hole is shortened, and an impedance is lowered.