LCD Peripheral Circuit Marks Placement via Pitch Variation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in fabricating LCD panels lies in the difficulty of creating marks between traces in the peripheral circuit due to the decreasing line width and pitch, making it hard to accurately manufacture and recognize the positions of pins and circuit elements using conventional processes.
Innovation Solution
The active device array substrate features connecting lines arranged in different pitches, with marks placed between adjacent lines, allowing for the marks to be disposed without affecting existing designs, and utilizing the same material as the connecting lines to simplify fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the line width and pitch of peripheral circuit are decreased to increase pin count, then the driver IC packaging capability is improved, but the difficulty of fabricating marks between traces increases
Solution Approach 1:
The patent moves the marks from the traditional position between traces in the peripheral circuit area to the active area where pixel electrodes are located. Specifically, marks are formed at the same positions as the pixel electrodes, allowing them to be fabricated simultaneously with the pixel electrodes during the same manufacturing process step, thus avoiding the constraint of minimum trace pitch
Solution Approach 2:
The pixel electrode pattern is formed first, and the marks are formed at the same time as the pixel electrodes. This preliminary formation of marks along with the pixel electrodes eliminates the need for subsequent mark fabrication processes that would be constrained by the reduced trace pitch
2Measurement precision
If marks are formed between traces in peripheral circuit, then position marking function is achieved, but the mark width becomes smaller than manufacturing capability
Solution Approach 1:
The patent relocates marks from the constrained peripheral circuit area to the active area, positioning them at the same locations as pixel electrodes. This allows marks to have sufficient width (at least 12 microns) since they are formed alongside pixel electrodes rather than being constrained by the 22-micron or 9-micron trace pitch in the peripheral circuit
Solution Approach 2:
The patent combines the formation of marks with the formation of pixel electrodes. Both are created in the same manufacturing step using the same process, so the mark width is determined by the pixel electrode dimensions rather than the trace pitch, making mark fabrication feasible with existing manufacturing capabilities
Data Source
AI summary
An active device array substrate includes a substrate, a pixel array, a peripheral circuit, and a number of marks. The substrate has an active area and a peripheral circuit area that is connected to the active area. The pixel array is disposed on the active area of the substrate. The peripheral circuit is disposed on the peripheral circuit area of the substrate. Besides, the peripheral circuit includes a number of driver bonding pads, a number of fan-out lines, and a number of connecting lines. The fan-out lines are electrically connected to the pixel array. Each of the connecting lines connects one of the driver bonding pads and one of the fan-out lines. Additionally, the connecting lines are arranged in different pitches. Each of the marks is disposed between two adjacent connecting lines.