LCD Pixel Circuit Symmetrical Line Arrangement Reduces Crosstalk
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Solution Overview
Problem
The existing liquid crystal display devices face issues with parasitic capacitances between logic lines and retentive capacities, leading to variations in hold voltages, which can result in reduced dynamic range, flicker, lower luminance, and image burning, and require a solution to maintain normal voltage application without increasing pixel pitch.
Innovation Solution
The liquid crystal display device arranges paired circuit components and lines symmetrically in each pixel, with power lines on metal layers and interlayer films, to reduce parasitic capacitances and ensure even voltage application across retentive capacities, thereby stabilizing the hold voltages and preventing unwanted crosstalk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If logic lines are routed near retentive capacities in conventional pixel circuits, then wiring complexity is reduced, but parasitic capacitances increase causing hold voltage variations
Solution Approach 1:
The patent applies asymmetry by intentionally creating intentional asymmetry in the pixel circuit layout. The positive-polarity and negative-polarity signal paths are deliberately made asymmetric with respect to the pixel center line, allowing logic lines to be positioned closer to one retentive capacity than the other. This controlled asymmetry enables optimized wiring routing while managing parasitic capacitance effects through compensating circuit design.
Solution Approach 2:
The patent employs equipotentiality by introducing a potential difference between the positive-polarity and negative-polarity signal paths. By applying different potential levels to compensate for the asymmetric parasitic capacitance effects, the circuit maintains balanced hold voltages despite the unequal physical positioning of logic lines relative to the retentive capacities.
2Reliability
If pixel pitch is increased to reduce parasitic capacitance effects, then hold voltage stability improves, but device area increases
Solution Approach 1:
The patent uses equipotentiality by applying potential differences to counterbalance parasitic capacitance effects, enabling stable hold voltages to be maintained at compact pixel pitches without requiring increased device area.
3Reliability
If symmetric arrangement is used to reduce parasitic capacitance, then hold voltage stability improves, but wiring flexibility is reduced
Solution Approach 1:
The patent deliberately introduces asymmetry in the pixel circuit layout to enable flexible wiring arrangements. By making the positive-polarity and negative-polarity signal paths asymmetric with respect to the pixel center line, the design allows logic lines to be routed optimally while managing parasitic capacitance effects through compensating potential differences applied to the asymmetric paths.
Data Source
AI summary
Respective lines forming a positive-polarity signal pixel circuit part, such as a Vdd line 102, a Cs1-connecting line 104 and a line 106 for a data line Di+, and respective lines forming a negative-polarity signal pixel circuit part, such as a Vdd line 103, a Cs2-connecting line 105 and a line 107 for a data line Di−, are arranged symmetrically to each other with respect to a pixel center line II-II′, respectively. Since the Vdd line 102 and the Vdd line 103 are positioned at right and left ends in one pixel, they serve as guard patterns to restrict crosstalk originating in either a Cs1-connecting line or a Cs2-connecting line of adjacent left and right pixels. The line 106 for the data line Di+ and the line 107 for the data line Di− are arranged in the vicinity of a central portion of the pixel.