LCD Pixel Structure Layout for Vertical Crosstalk Cancellation
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Solution Overview
Problem
Ultra-high-definition liquid crystal displays with narrow bezels suffer from vertical crosstalk due to parasitic capacitance between data lines and pixel units, causing instability and quality issues, as the chip-on-film package method leads to uneven parasitic capacitance and interference.
Innovation Solution
A pixel structure with a first and second pixel electrode, transverse and longitudinal signal lines arranged in a specific configuration to cancel capacitive coupling, where the longitudinal signal lines are oppositely oriented and symmetrical to the pixel electrodes, reducing capacitive coupling and improving display performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If chip-on-film package method is used for gate drivers with data lines and scan lines on the same side, then bezel width is reduced achieving ultra-narrow bezel effects, but parasitic capacitance between data lines and pixel units increases causing vertical crosstalk
Solution Approach 1:
The patent introduces compensation signal lines that generate compensation signals to counteract the harmful parasitic capacitance effects. By deliberately introducing additional signal lines with controlled parasitic capacitance, the harmful coupling effect is converted into a beneficial compensation mechanism that cancels out the vertical crosstalk, allowing ultra-narrow bezel design to be maintained without display quality degradation
Solution Approach 2:
The patent employs asymmetric arrangement of compensation signal lines relative to the data lines, where the compensation signal lines are positioned at different distances from the pixel units compared to the original data lines. This asymmetric configuration creates differential parasitic capacitance that can be used to compensate for the uneven coupling effects in the ultra-narrow bezel structure
2Measurement precision
If pixel units are increased in resolution and decreased in size for ultra-high-definition display, then display resolution is improved, but coupling of parasitic capacitance between data lines and pixel units becomes more significant
Solution Approach 1:
The patent applies different configurations of compensation signal lines to different regions of the display panel. By locally adjusting the position and arrangement of compensation signal lines in different pixel unit regions, the parasitic capacitance compensation is optimized for each specific location, addressing the increased coupling effects that result from smaller pixel sizes in ultra-high-definition displays
Solution Approach 2:
The compensation signal lines act as intermediary elements between the data lines and pixel units. These intermediary signal lines provide a controlled parasitic capacitance path that mediates the coupling interaction, allowing the harmful direct coupling between data lines and pixel units to be transformed into a manageable and compensatable effect
3Ease of manufacture
If data lines are configured on left and right sides of pixel units with different distances to pixel unit electrodes, then chip-on-film package structure is achieved, but differences in parasitic capacitance prevent complete elimination of interference through opposite signal setting
Solution Approach 1:
The patent divides the signal compensation function into multiple segments by introducing separate compensation signal lines for different regions. Instead of relying on a single symmetric configuration, the compensation is segmented into multiple independent signal paths, each tailored to compensate for the specific parasitic capacitance characteristics of adjacent pixel units, thereby addressing the asymmetry in the chip-on-film package structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively eliminates vertical crosstalk and enhances display performance by minimizing capacitive coupling between signal lines and pixel electrodes, improving image quality and aperture ratio.
Implementation Method 1
cancel capacitive coupling between the first longitudinal signal line and the second longitudinal signal line and the first pixel electrode
Implementation Method 2
parasitic capacitance between data lines and pixel units
Data Source
AI summary
A pixel structure and a display panel are provided. The pixel structure includes a first pixel electrode, a first longitudinal signal line, and a second longitudinal signal line. The first pixel electrode includes a first main pixel area and a first sub-pixel area. The first longitudinal signal line includes a first main line and a first secondary-line. The second longitudinal signal line includes a second main line and a second secondary-line. The first main line and the second main line are arranged in the first main pixel area, and the first secondary-line and the second secondary-line are arranged in the first sub-pixel area.