IPS LCD Pixel Electrode Overlap Gate Signal Lines
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Solution Overview
Problem
In IPS liquid crystal display devices, parasitic capacitors between pixel electrodes and data signal lines cause display unevenness and reduce the aperture ratio, with traditional methods to mitigate this issue, such as increasing the distance between electrodes, compromising the pixel's aperture ratio.
Innovation Solution
The design involves a configuration where the pixel electrode overlaps gate signal lines, with a smaller interline pitch for data signal lines than gate signal lines, and strategically overlapping areas to reduce parasitic capacitance while maintaining or improving the aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the distance between the pixel electrode and the two data signal lines is increased to reduce parasitic capacitance, then display unevenness is reduced, but the aperture ratio of the pixel is reduced
Solution Approach 1:
The patent introduces a third dimension by having the pixel electrode overlap with gate signal lines in the row direction (vertical dimension in plan view). This vertical overlap creates additional capacitance that compensates for the reduced parasitic capacitance from increased horizontal distance, thereby maintaining display uniformity while preserving aperture ratio.
Solution Approach 2:
The patent changes the spatial arrangement parameters by setting the interline pitch of gate signal lines to be smaller than that of data signal lines. This parameter difference allows the pixel electrode to strategically overlap with gate signal lines, creating controlled capacitance relationships that resolve the contradiction between reducing parasitic capacitance and maintaining aperture ratio.
2Area of stationary object
If the interline pitch of gate signal lines is made smaller than data signal lines to enable pixel electrode overlap, then aperture ratio is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by creating different interline pitch characteristics in different regions: smaller pitch for gate signal lines where overlap is needed, and larger pitch for data signal lines where parasitic capacitance reduction is prioritized. This localized differentiation allows the pixel electrode to achieve optimal overlap with gate signal lines while maintaining ease of manufacture through standard photolithography processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces display unevenness and enhances the aperture ratio of the pixel by minimizing parasitic capacitance and optimizing the overlap areas between pixel electrodes and signal lines.
Implementation Method 1
a parasitic capacitor is liable to be formed between a pixel electrode and two data signal lines adjacent thereto on the right and on the left
Implementation Method 2
an electric field in a direction parallel to the substrate (lateral electric field) is generated between the pixel electrode and the common electrode so that the lateral electric field is applied to the liquid crystal to drive the liquid crystal
Data Source
AI summary
Provided is a liquid crystal display device, including: a first substrate and a second substrate. On the second substrate, a plurality of gate signal lines, a plurality of data signal lines, a plurality of pixel electrodes provided correspondingly to a plurality of pixels, and a common electrode provided so as to be opposed to the pixel electrodes are formed. An interline pitch of the gate signal lines is smaller than an interline pitch of the data signal lines. In each of the pixels, the pixel electrode overlaps, in plan view, gate signal lines adjacent to the pixel electrode.