LCD Pixel Electrode Layout With Loop Scan Line to Cut Parasitic Capacitance
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Solution Overview
Problem
As liquid crystal display devices increase in size and resolution, the number of pixels grows, leading to shorter writing times and increased parasitic capacitance and wiring resistance, which results in display quality issues such as unevenness, grayscale defects, and higher power consumption.
Innovation Solution
The design incorporates a pixel structure with a signal line and a scan line intersecting, where the scan line has a loop shape with an opening, allowing the first electrode to be partially overlapped with the opening, reducing parasitic capacitance while maintaining a high aperture ratio and preventing increased wiring resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of pixels is increased to achieve larger screen size and higher definition, then display quality and resolution are improved, but parasitic capacitance and wiring resistance increase causing signal transmission delay and display unevenness
Solution Approach 1:
The scan line is divided into multiple segments forming a loop shape with openings, rather than a continuous straight line. This segmentation reduces the overlapping area between scan lines and electrode patterns, thereby reducing parasitic capacitance while maintaining signal transmission capability across the high-resolution display panel
Solution Approach 2:
The scan line is transformed from a one-dimensional straight line into a two-dimensional loop structure with openings. This dimensional change allows the scan line to bypass certain areas, reducing overlap with electrode patterns and minimizing parasitic capacitance effects in high-resolution displays
2Reliability
If the scan line width is increased to reduce wiring resistance, then signal transmission is improved, but parasitic capacitance between scan line and electrode increases
Solution Approach 1:
The scan line is segmented into multiple sections forming a loop with openings. This allows the scan line to maintain adequate width for low resistance in critical sections while creating gaps in other sections to reduce parasitic capacitance overlap with electrode patterns
Solution Approach 2:
Different sections of the scan line have different geometries: some sections are wider to reduce resistance, while other sections form openings to reduce parasitic capacitance. This local variation in geometry optimizes both electrical properties simultaneously
3Illumination intensity
If the aperture ratio is increased to improve display brightness, then light transmission is improved, but the area for electrode overlap with scan line increases causing higher parasitic capacitance
Solution Approach 1:
The loop-shaped scan line with openings segments the overlapping area between scan line and electrode. This segmentation reduces the total overlap area, thereby reducing parasitic capacitance while maintaining a large aperture ratio for high display brightness
Data Source
AI summary
To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.