LCD Pixel Structure Mask Reduction via Complementary Projections

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The existing liquid crystal display (LCD) manufacturing processes require six masks, which increases the time and complexity of new product development and design costs.

Innovation Solution

A method for forming a pixel structure that reduces the number of masks needed by using a single mask pattern for both the semiconductor and common electrode layers, simplifying the manufacturing process and design.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If six masks are used in general LCD manufacturing processes, then the manufacturing precision and reliability are maintained, but the device complexity and loss of time increase

Engineering Contradiction:
Improvepattern accuracyVSAvoidmask quantity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent merges the patterning steps for the semiconductor layer and common electrode layer into a single exposure step using one mask. The mask contains both the semiconductor pattern and common electrode pattern, allowing both layers to be patterned simultaneously, thereby reducing the mask quantity from six to fewer while maintaining pattern accuracy

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single mask serves multiple functions by containing patterns for both the semiconductor layer and common electrode layer. This multi-functional mask replaces multiple dedicated masks, reducing device complexity and the number of exposure steps while maintaining the required manufacturing precision for each layer

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Manufacturing precision

If six masks are used in general LCD manufacturing processes, then the manufacturing precision is maintained, but the loss of time increases

Engineering Contradiction:
Improvepattern accuracyVSAvoidnew product development time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent combines multiple patterning operations into a single exposure step. By placing both semiconductor and common electrode patterns on one mask, the manufacturing process requires fewer exposure steps, directly reducing the time for new product development while maintaining pattern accuracy through precise mask design and alignment

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The mask is designed in advance to contain all necessary patterns for both semiconductor and common electrode layers. This preliminary preparation of a multi-pattern mask eliminates the need for sequential mask changes and multiple exposure steps, thereby reducing development time while ensuring pattern accuracy is maintained

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the time and cost associated with new product development and design, while maintaining the integrity of the pixel structure by ensuring that the semiconductor and common electrode layers are accurately patterned with complementary orthogonal projections.

Implementation Method 1

coating a first photoresist layer on the semiconductor layer; exposing and developing the first photoresist layer to form a first photoresist pattern

Methodology Applied
Scientific EffectPhotoresist exposure and development: Photopolymerisation

Data Source

PatentUS10177180B2Method for forming pixel structure
Publication Date: 2019.01.08 CHUNGHWA PICTURE TUBES LTD
  • US10177180B2 patent drawing
  • US10177180B2 patent drawing
  • US10177180B2 patent drawing

AI summary

A method for forming a pixel structure is provided. The method includes: forming a gate electrode layer on a substrate; forming a first insulating layer on the gate electrode layer and the substrate; forming a semiconductor layer on the first insulating layer; forming a pixel electrode layer on the first insulating layer and the semiconductor layer; forming a source/drain electrode layer on the pixel electrode layer, the semiconductor layer, and the first insulating layer; forming a second insulating layer on the semiconductor layer, the pixel electrode layer, the source/drain electrode layer, and the first insulating layer; and forming a common electrode layer on the second insulating layer, in which an orthogonal projection of the semiconductor layer on the substrate is complementary to an orthogonal projection of the common electrode layer on the substrate.