LCD Pixel Parasitic Capacitance Uniformity
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Solution Overview
Problem
Liquid crystal display (LCD) devices experience non-uniform brightness due to delays in gate signals, which result in varying kickback voltages and subsequent brightness differences across the screen, especially noticeable in larger displays.
Innovation Solution
The design adjusts the parasitic capacities between the gate and source/drain electrodes, as well as the storage capacity, by modifying the overlap areas of the electrodes and distributing these capacities uniformly towards the gate driver, thereby reducing the ratio of parasitic capacities and ensuring consistent kickback voltages across pixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the gate lines are made longer to cover more pixels, then the display area is increased, but the gate signal delay increases causing non-uniform brightness
Solution Approach 1:
The patent applies local quality by making the parasitic capacity distribution non-uniform across different pixel regions. Specifically, pixels closer to the gate driver have different parasitic capacity characteristics compared to pixels farther away, allowing each region to be optimized for its specific position in the gate signal propagation path, thereby compensating for position-dependent delays.
Solution Approach 2:
The patent changes the parasitic capacity parameter across different pixel locations. By adjusting the overlap area between gate and source/drain electrodes, the parasitic capacity is varied spatially to compensate for gate signal delays, ensuring uniform kickback voltages and brightness across the entire display.
2Illumination intensity
If the parasitic capacity is increased to reduce kickback voltage, then brightness uniformity is improved, but the storage capacity is reduced
Solution Approach 1:
The patent applies local quality by making the parasitic capacity distribution non-uniform across different pixel regions. Specifically, pixels closer to the gate driver have different parasitic capacity characteristics compared to pixels farther away, allowing each region to be optimized for its specific position in the gate signal propagation path, thereby compensating for position-dependent delays.
Solution Approach 2:
The patent changes the parasitic capacity parameter across different pixel locations. By adjusting the overlap area between gate and source/drain electrodes, the parasitic capacity is varied spatially to compensate for gate signal delays, ensuring uniform kickback voltages and brightness across the entire display.
3Quantity of substance
If the overlap area between gate and source/drain electrodes is increased, then parasitic capacity is increased, but the device complexity increases
Solution Approach 1:
The patent applies local quality by making the parasitic capacity distribution non-uniform across different pixel regions. Specifically, pixels closer to the gate driver have different parasitic capacity characteristics compared to pixels farther away, allowing each region to be optimized for its specific position in the gate signal propagation path, thereby compensating for position-dependent delays.
Solution Approach 2:
The patent changes the parasitic capacity parameter across different pixel locations. By adjusting the overlap area between gate and source/drain electrodes, the parasitic capacity is varied spatially to compensate for gate signal delays, ensuring uniform kickback voltages and brightness across the entire display.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach leads to more uniform brightness across the LCD screen by minimizing the difference in kickback voltages, enhancing display quality and reducing the impact of gate signal delays.
Implementation Method 1
Orientation of liquid crystal molecules in the liquid crystal layer is determined by an electric filed between the pixel voltage Vp charged in the pixels and a common voltage on the common electrode
Implementation Method 2
The data voltage Vd applied to the pixels is reduced by parasitic capacity Cp between the gate electrode and the source electrode (drain electrode) to form the pixel voltage Vp
Data Source
AI summary
A liquid crystal display device includes a first substrate which comprises a plurality of pixels where a thin film transistor and a pixel electrode electrically connected to the thin film transistor are formed, the first substrate including a gate line and a data line which insulatingly intersect each other; and a gate driver which applies a gate driving signal to the gate line, the thin film transistor including a gate electrode which is connected to the gate line; a source electrode which is connected to the data line; and a drain electrode which is connected to the pixel electrode, and the pixels being decreased in a value of Cp/(Cp+Clc+Cst) as going toward the gate driver (where, Cp: a sum of parasitic capacity between the gate electrode and the source electrode and parasitic capacity between the gate electrode and the drain electrode, Clc: liquid crystal capacity, and Cst: storage capacity).