LCD Pixel SRAM DRAM Timing Control Peak Current
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Solution Overview
Problem
Conventional LCD devices employing the sub frame drive scheme face challenges in reducing pixel size due to the large number of transistors and experience high consumption current peaks, leading to voltage drops and image distortion during gradation display.
Innovation Solution
The LCD device incorporates a pixel configuration with a static dynamic random access memory (SRAM) for sub frame data sampling and a dynamic random access memory (DRAM) for output, along with a timing control unit that delays the activation of switching units, reducing instantaneous current consumption and stabilizing power voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a two-stage master latch configuration with SRAM is used for sub frame drive scheme, then gradation display is achieved, but the number of transistors increases and pixel size cannot be reduced
Solution Approach 1:
The patent extracts the data holding function from the complex two-stage SRAM latch structure and implements it using a simpler single-stage latch configuration combined with a capacitor. This extraction reduces the transistor count while maintaining the gradation display capability through the capacitor's ability to hold voltage levels representing different gradation states.
Solution Approach 2:
The patent changes the fundamental parameter of data storage from magnetic/electric state in SRAM to voltage charge state in a capacitor. This parameter change allows the same gradation display function to be achieved with fewer transistors, as the capacitor naturally holds voltage levels without requiring the complex latch circuitry of SRAM.
2Productivity
If all pixels are read out simultaneously during sub frame switching, then data is transferred to slave latch, but instantaneous current consumption peaks causing voltage drops
Solution Approach 1:
The patent segments the simultaneous readout operation of all pixels into sequential or staggered readout operations. By dividing the pixel array into groups that are read out at different times, the instantaneous current demand is reduced while the overall data transfer productivity is maintained through the sub frame timing structure.
Solution Approach 2:
The patent implements periodic readout actions where pixels are read out in alternating sub frames rather than all at once. This periodic action spreads the current consumption over time, preventing instantaneous peaks while maintaining the required data transfer rate through the sub frame drive scheme's inherent timing.
Data Source
AI summary
A LCD device includes pixels formed of column data lines and row scanning lines. The pixel includes a display element; a first switching unit that performs sampling on each frame data of an input video signal; a first holding unit that configures an SRAM, and holds sub frame data; a second switching unit that causes the sub frame data held in the first holding unit; and a second holding unit that configures a DRAM, and applies output data to the pixel electrode, a pixel control unit that performs an operation of repeating writing the sub frame data in the first holding unit, turning on the second switching units, and rewriting memory content of the second holding units; and a timing control unit. A delay of a certain period of time is sequentially given to a timing at which the pixel control unit turns on the second switching unit.