Liquid Crystal Pixel Array Storage Capacitor Layout
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Solution Overview
Problem
The reduction in aperture ratio of liquid crystal displays due to the formation of storage capacitors near gate lines, which affects voltage hold strength and increases parasitic capacitance, leading to a compromise in display performance.
Innovation Solution
The storage capacitors are positioned in a storage area between adjacent pixels, farthest from the data lines and gate lines, allowing for a reduced formation area and minimizing parasitic capacitance influence, thereby enhancing voltage hold strength and aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the storage capacitor is formed near the gate line to hold data voltage, then the voltage hold strength is improved, but the aperture ratio is reduced due to increased parasitic capacitance
Solution Approach 1:
The storage capacitor is extracted from its conventional position near the gate line and relocated to a dedicated storage area between adjacent pixels. This separation removes the storage capacitor from the harmful electromagnetic environment of the gate line, reducing parasitic capacitance while preserving voltage hold strength.
Solution Approach 2:
The storage capacitor is positioned in a previously underutilized spatial dimension - the vertical space between adjacent pixels in the pixel array. This dimensional reorganization allows the storage capacitor to occupy space that does not interfere with the aperture ratio of individual pixels.
2Reliability
If the storage capacitor area is increased to compensate for parasitic capacitance, then the voltage hold strength is improved, but the aperture ratio is further reduced
Solution Approach 1:
By extracting the storage capacitor from the gate line proximity, the invention eliminates the need to increase capacitor area to compensate for parasitic effects. The storage capacitor achieves sufficient voltage hold strength at optimal area without the area penalty imposed by gate line interference.
3Ease of manufacture
If the storage capacitor is positioned close to data lines and gate lines, then the manufacturing layout is simplified, but parasitic capacitance increases reducing voltage hold strength
Solution Approach 1:
The display structure is segmented into distinct functional zones: pixel electrode areas, gate line areas, data line areas, and a dedicated storage area. This spatial segmentation allows each component to be optimized for its specific function without interference from other components.
Solution Approach 2:
The storage area acts as an intermediary zone between adjacent pixels, providing a dedicated space for storage capacitors that is electrically isolated from data lines and gate lines. This intermediary positioning reduces parasitic capacitance while maintaining manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the aperture ratio by reducing the impact of parasitic capacitance and maintaining desired voltage hold strength, while also allowing for a more efficient layout of signal lines, thus enhancing overall display performance.
Implementation Method 1
a first storage capacitor Cst1 for holding the first data voltage during a predetermined period
Implementation Method 2
controlling an electric field applied to liquid crystal molecules based on a data voltage
Data Source
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AI summary
A pixel array of a liquid crystal display is discussed. The pixel array can include a first pixel including a first pixel electrode charged to a first data voltage, an upper common electrode which is positioned opposite the first pixel electrode and forms an electric field, a lower common electrode applying a common voltage to the upper common electrode, and a first storage capacitor for holding the first data voltage during a predetermined period, and a second pixel including a second pixel electrode charged to a second data voltage, the upper common electrode, the lower common electrode, and a second storage capacitor for holding the second data voltage during a predetermined period. The first and second storage capacitors are located in a storage area between the first and second pixels, which are positioned adjacent to each other in a horizontal direction.