LCD Pixel Wiring Layout to Cut Parasitic Capacitance
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Solution Overview
Problem
Large-sized liquid crystal display devices with high resolution face issues of increased parasitic capacitance and wiring resistance, leading to display unevenness, grayscale defects, and higher power consumption.
Innovation Solution
The design incorporates a loop-shaped scan line with an opening, where the first electrode is partially located within the opening, reducing overlap area with the scan line and maintaining a higher aperture ratio, thereby minimizing parasitic capacitance and wiring resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the screen size is increased to 60 inches or more and resolution is improved to HD or FHD, then the display quality is improved, but the number of pixels is significantly increased causing writing time for one pixel to be shortened and requiring high speed operation and high on-current thin film transistors
Solution Approach 1:
The patent changes the geometric parameters of the scan line by forming it with a loop shape including an opening, and positioning the first electrode within this opening. This parameter change reduces the overlap area between the scan line and first electrode, thereby reducing parasitic capacitance and allowing for faster pixel writing times in high-resolution displays.
2Manufacturing precision
If the screen size is increased to 60 inches or more and resolution is improved to HD or FHD, then the display quality is improved, but the wiring resistance and parasitic capacitance between wirings are increased causing delay of signal transmission and deterioration of display quality
Solution Approach 1:
The patent changes the geometric parameters of the scan line by forming it with a loop shape including an opening, and positioning the first electrode within this opening. This parameter change reduces the overlap area between the scan line and first electrode, thereby reducing parasitic capacitance and allowing for faster pixel writing times in high-resolution displays.
3Area of stationary object
If the overlap area between scan line and first electrode is increased, then the aperture ratio is improved, but the parasitic capacitance between wirings is increased causing delay of signal transmission and increase in power consumption
Solution Approach 1:
The patent changes the geometric parameters of the scan line by forming it with a loop shape including an opening, and positioning the first electrode within this opening. This parameter change reduces the overlap area between the scan line and first electrode, thereby reducing parasitic capacitance while maintaining acceptable aperture ratio for high-resolution displays.
Data Source
AI summary
To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.