LCD Pull-Down Signal Line Layout to Prevent Photoresist Peeling

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Solution Overview

Problem

The photoresist on the pull-down unit in existing liquid crystal display devices is easily peeled off during wet etching, leading to disconnection and failure of the pull-down unit, which results in abnormal display.

Innovation Solution

The liquid crystal display panel design includes a pull-down signal line with a first and second portion, spaced apart from gate layer projections, and connected by a connection line, ensuring the photoresist thickness matches other areas, preventing peeling and allowing for increased width without additional metals under the signal line.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the pull-down unit height is increased to improve color shift, then the voltage control precision is improved, but the photoresist thickness on the pull-down unit becomes relatively thin, making the photoresist prone to peeling during wet etching

Engineering Contradiction:
Improvevoltage control precisionVSAvoidphotoresist adhesion
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent applies local quality by introducing a gate insulating layer specifically in the area corresponding to the pull-down signal line, where it directly contacts the substrate. This localized structural modification ensures uniform photoresist thickness only in the critical pull-down region, while other areas maintain their original design. The gate insulating layer acts as a filler that eliminates the height difference, allowing the photoresist to adhere properly without peeling during wet etching processes.

Inventive Principle:
Principle #3Local quality

2Reliability

If the photoresist thickness is increased to prevent peeling, then the photoresist adhesion is improved, but the manufacturing process complexity increases

Engineering Contradiction:
Improvephotoresist adhesionVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by forming the gate insulating layer in advance, before the photoresist coating step. This pre-prepared insulating layer creates a uniform surface that ensures adequate photoresist thickness and adhesion from the outset, eliminating the need for subsequent process modifications or repairs. The gate insulating layer is deposited as part of the existing manufacturing sequence, integrating smoothly without adding significant process complexity.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If the pull-down signal line width is increased to reduce impedance, then the electrical conductivity is improved, but the manufacturing precision requirements increase

Engineering Contradiction:
Improveelectrical conductivityVSAvoidline width control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies parameter changes by modifying the physical state of the substrate surface in the pull-down region through the addition of a gate insulating layer. This changes the effective height parameter locally, allowing the pull-down signal line to achieve adequate photoresist coverage and adhesion. The insulating layer's dielectric properties also help maintain electrical isolation while permitting broader line width variations without compromising manufacturing precision or electrical performance.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12560845B2Liquid crystal display panel, manufacturing method thereof, and liquid crystal display device
Publication Date: 2026.02.24 SHENZHEN CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
  • US12560845B2 patent drawing
  • US12560845B2 patent drawing
  • US12560845B2 patent drawing

AI summary

The present disclosure provide a liquid crystal display panel, a manufacturing method thereof, and a liquid crystal display device. In the liquid crystal display panel, a projection of the pull-down signal line on the substrate is spaced apart from a projection of any wiring in the gate layer on the substrate, so that no other metal is placed under the pull-down signal line, and the thickness of the photoresist on the pull-down signal line can be increased accordingly, thus the width of the pull-down signal line can be increased, and disconnection and failure of the pull-down signal line can be avoided.