Liquid Crystal Pixel Scan Line Loop Reduces Parasitic Capacitance
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Solution Overview
Problem
As liquid crystal display devices increase in size and resolution, the need for high-speed operation of thin film transistors, reduced parasitic capacitance, and minimized wiring resistance becomes crucial to maintain display quality and reduce power consumption.
Innovation Solution
The implementation of a pixel structure in liquid crystal display devices, where part of the scan line has a loop shape with an opening, and the first electrode is located in this opening, reduces parasitic capacitance between the scan line and the first electrode while preventing increases in wiring resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the screen size and resolution are increased, then the display quality is improved, but the parasitic capacitance between wirings increases and writing time per pixel is reduced
Solution Approach 1:
The scan line is divided into multiple segments with different widths. Specifically, the scan line includes a first portion with a first width and a second portion with a second width that is greater than the first width. This segmentation allows different regions of the scan line to serve different functions: narrower regions reduce parasitic capacitance while wider regions maintain signal strength and reduce resistance over longer distances.
Solution Approach 2:
Different portions of the scan line are assigned different local properties (widths) according to their specific functional requirements. The wider second portion is strategically placed where longer wiring distances require reduced resistance, while the narrower first portion is used where parasitic capacitance reduction is more critical. This local optimization resolves the contradiction between reducing capacitance and maintaining signal integrity.
2Speed
If the parasitic capacitance between wirings is reduced, then the writing speed is improved, but the wiring resistance may increase
Solution Approach 1:
The scan line is segmented into portions with different widths to simultaneously address capacitance reduction and resistance control. By dividing the scan line into multiple segments with optimized widths, the design achieves both faster writing speeds (through reduced capacitance) and maintained signal reliability (through strategically placed wider sections with lower resistance).
Solution Approach 2:
The width parameter of the scan line is varied across different portions rather than maintaining a uniform width. This parameter change allows the scan line to optimize for capacitance reduction in certain regions while compensating for resistance increases in other regions, thereby achieving both improved writing speed and maintained reliability.
Data Source
AI summary
To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.