Liquid Crystal Display Semiconductor Etching Profile Control
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Solution Overview
Problem
Large and high-quality liquid crystal displays face issues with deteriorated display quality due to inclined semiconductor surfaces and protruded portions during the thin film transistor formation process, leading to leakage currents and washed-out color defects.
Innovation Solution
The liquid crystal display design minimizes semiconductor pattern protrusions and channel steps through precise etching techniques, ensuring the semiconductor layer's channel step is less than 50 Å and the protruded part width is less than 1.3 μm, using a method that excludes chlorine in dry etching to prevent leakage currents and maintain display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching techniques are used to form semiconductor patterns, then manufacturing efficiency is maintained, but protruded portions and inclined surfaces are created leading to deteriorated display quality
Solution Approach 1:
The patent changes the etching parameters by excluding chlorine from the dry etching process and using specific gas ratios (CHF3:CF4 = 1:4 to 1:10), which fundamentally alters the etching mechanism to prevent protruded portions and inclined surfaces while maintaining manufacturing efficiency
Solution Approach 2:
The patent applies a slightly excessive etching depth control by limiting the channel step to 50 Å or less, which requires precise control but ensures that protruded portions do not overlap with data conductors, thereby preventing display quality deterioration
2Reliability
If semiconductor layer channel step is reduced to prevent leakage current, then electrical characteristics improve, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the etching chemistry by using fluorine-based gases without chlorine, which produces a different etching profile that naturally limits the channel step to 50 Å or less, improving electrical characteristics while the precision is achieved through gas ratio control rather than complex process steps
Solution Approach 2:
The patent introduces a specific gas mixture ratio (CHF3:CF4 = 1:4 to 1:10) as an intermediary parameter that mediates between etching speed and channel step control, allowing precise channel step limitation without requiring extreme manufacturing precision
3Manufacturing precision
If protruded part width is minimized to prevent waterfall phenomenon, then display quality improves, but etching process control becomes more difficult
Solution Approach 1:
The patent changes the fundamental etching chemistry by excluding chlorine and using fluorine-based gases with specific ratios, which inherently produces vertical sidewalls and minimizes protruded part width to 1.3 μm or less without requiring complex multi-step etching processes
Solution Approach 2:
The patent replaces complex mechanical/multistep etching control mechanisms with a chemically-driven single-step etching process using fluorine-based gases, which automatically achieves the required protruded part width control through the etching chemistry itself
Data Source
AI summary
A liquid crystal display includes: a gate line connected to a gate electrode; a semiconductor layer disposed on the gate line and including silicon; an ohmic contact layer disposed on the semiconductor layer; and a data conductor disposed on the ohmic contact layer. The semiconductor layer includes a source region, a drain region, and a channel region disposed between the source region and the drain region. The data conductor includes a data line transmitting a data signal, a source electrode corresponding to the source region, and a drain electrode corresponding to the drain region. A channel step of the semiconductor layer is a height difference between an upper surface in the source region or the drain region and an upper surface in the channel region. The upper surface in the source region or the drain region has a maximum height of the semiconductor layer.


