LCD Shift Register Circuit to Mitigate TFT Gate Bias Stress
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Solution Overview
Problem
Amorphous silicon thin film transistors in liquid crystal display shift registers experience gate bias stress due to continuous direct current voltage, leading to erroneous operations such as multiple output generation, as the threshold voltage change reduces the clamping voltage applied to the gate node.
Innovation Solution
A shift register design with dual pull-down transistors driven alternately at odd and even frames, using inverted clock signals and driving voltages to minimize direct current bias stress, and employing a diode configuration for transistors connected to supply lines to manage voltage states effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single pull-down transistor is used in the shift register stage, then the circuit complexity is reduced, but gate bias stress occurs due to continuous direct current voltage leading to threshold voltage change and erroneous operations
Solution Approach 1:
The single pull-down transistor is segmented into two separate pull-down transistors (first pull-down transistor and second pull-down transistor) that operate alternately. This segmentation allows the direct current voltage to be distributed across different transistors in different frames, preventing continuous bias stress on a single transistor while maintaining circuit functionality.
Solution Approach 2:
The two pull-down transistors are activated periodically in alternating frames rather than continuously. The first pull-down transistor operates in odd frames while the second operates in even frames, creating a periodic action pattern that eliminates continuous direct current bias stress on any single transistor, thereby preventing threshold voltage drift and ensuring reliable operation.
2Stability of the object's composition
If direct current voltage is continuously supplied to the transistor gate terminal, then the transistor maintains stable operation, but gate bias stress occurs causing threshold voltage change and multiple output generation
Solution Approach 1:
The direct current voltage supply to the transistor gate terminal is converted from continuous to periodic through the alternating frame operation of two pull-down transistors. Each transistor receives direct current voltage only during its active frames (first transistor in odd frames, second transistor in even frames), creating periodic voltage application that prevents continuous bias stress accumulation while maintaining operational stability.
Solution Approach 2:
The system discards the continuous direct current voltage application to a single transistor and recovers functionality by implementing periodic voltage application to alternating transistors. This allows the voltage stress to be discarded from one transistor while being applied to another, preventing threshold voltage degradation and ensuring reliable output signals.
3Ease of manufacture
If the shift register is fabricated using amorphous silicon thin film transistors, then manufacturing cost is reduced, but gate bias stress causes threshold voltage change leading to erroneous operations
Solution Approach 1:
The periodic alternating frame operation of two pull-down transistors is specifically designed to address the sensitivity of amorphous silicon thin film transistors to bias stress. This periodic action pattern ensures that no single transistor experiences continuous direct current voltage, preventing threshold voltage drift that would otherwise cause erroneous operations in low-cost amorphous silicon-based displays.
Data Source
AI summary
Disclosed is a shift register capable of mitigating gate bias stress. The shift register, including a plurality of stages, includes an output buffer having a pull-up transistor and two pull-down transistors, each with gates connected to different nodes. One of the two pull-down transistors operates during an even frame portion of an LCD operation; and the other of the two pull-down transistors operates during an odd frame portion of the LCD display operation. Alternating operation of the pull-down transistors substantially mitigates gate stress, and substantially enables the shift register to be fabricated with amorphous silicon.