LCD Shift Register Clock Signal Driving Circuit

The patent divides the clock signal driving into two distinct types: first clock signals for driving shift register units during normal operation, and second clock signals with higher driving ability for triggering next-stage shift register units. This segmentation allows each signal type to be optimized for its specific function, with second clock signals having enhanced amplitude or pulse width to ensure reliable triggering in cold-start conditions.

The patent applies different clock signal characteristics to different parts of the shift register system. Specifically, second clock signals are applied locally at the output ends of shift register units to trigger next-stage units, while first clock signals are used for normal operation. This local differentiation ensures that the triggering function receives enhanced signal strength where needed without affecting the overall system complexity excessively.

The patent dynamically switches between first and second clock signals based on operational requirements. During cold-start or when triggering next-stage shift register units, second clock signals with higher driving ability are applied. During normal operation, first clock signals are used to reduce power consumption. This dynamic adaptation allows the system to optimize between cold-start performance and power consumption based on actual operational state.

The patent employs periodic switching between different clock signal types. Second clock signals are applied periodically when needed for triggering next-stage units or during cold-start conditions, while first clock signals are used during normal operation. This periodic alternation ensures that enhanced driving ability is available when required without maintaining high power consumption continuously.

The patent introduces intermediate signal conditioning circuits between the clock signal generation and the shift register units. These intermediate circuits include level shifters and pulse width modulators that gradually transition voltage levels and smooth signal changes. The intermediary circuits prevent sudden voltage jumps that would cause image flicker while still providing sufficient driving ability for reliable shift register triggering.

The patent carefully controls parameter changes in clock signals, specifically managing voltage amplitude and pulse width transitions. When switching between first and second clock signals, the system gradually adjusts voltage levels and pulse characteristics rather than making abrupt changes. This controlled parameter transition maintains response speed while preventing image flicker by avoiding sudden voltage changes.