Signal Control Device for LCD Data Skew Compensation

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Solution Overview

Problem

High definition display devices experience significant data skew between channels due to factors like circuit element characteristics and PCB patterns, which worsens as the number of channels increases, affecting image display quality.

Innovation Solution

A signal control device employing dual-port random access memory (RAM) data storage units that write data signals in synchronization with received clock signals and read them out simultaneously using a single clock signal, compensating for skew between channels by aligning data signals across multiple channels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple channels are used to transmit data signals in high definition display devices, then data transmission capacity is improved, but data skew between channels worsens

Engineering Contradiction:
Improvedata transmission capacityVSAvoiddata skew between channels
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by writing data signals from multiple channels into storage units in advance, before reading them out simultaneously. The storage units temporarily hold the data signals, allowing the system to compensate for transmission skew by aligning the timing of data from different channels before they are read out together, thus resolving the skew problem while maintaining high transmission capacity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces storage units as an intermediary component between the multiple data transmission channels and the output. These storage units act as a mediator that receives data signals from multiple channels at different times, holds them temporarily, and then releases them simultaneously, thereby eliminating the skew effect while preserving the high data transmission capacity of multiple channels

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the number of channels is increased to handle high definition data, then data transmission capability is improved, but skew between channels becomes more serious

Engineering Contradiction:
Improvedata transmission capabilityVSAvoidskew between channels
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The storage units perform preliminary action by pre-writing data signals from multiple channels in advance of the simultaneous read operation. This allows the system to accommodate the different arrival times of signals from multiple channels while ensuring they are all ready and aligned when read out together, thus maintaining reliability despite increased channel count

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The storage units serve as an intermediary that buffers and synchronizes data from multiple channels. By introducing this intermediate storage layer, the system can handle more channels with improved transmission capability while the storage units ensure reliable simultaneous output by compensating for the skew that naturally occurs with increased channel count

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8810497B2Signal control device, liquid crystal display having the same and signal control method using the same
Publication Date: 2014.08.19 SAMSUNG DISPLAY CO LTD
  • US8810497B2 patent drawing
  • US8810497B2 patent drawing
  • US8810497B2 patent drawing

AI summary

A signal controlling method for a display device for signal processing between an external system and a display panel that displays an image by receiving a signal from the external system. The method includes receiving N clock signals and N data signals synchronized with the N clock signals from the external system through N channels, N being a natural number no less than 2; writing the received N data signals in N storage units in order of reception time of the N data signals; extracting one clock signal from the N clock signals; and outputting the N data signals written in the N storage units simultaneously in synchronization with the extracted clock signal.