Two-Stage LCD Source Driver DAC for High Resolution in Less Area
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Solution Overview
Problem
Conventional DAC architectures for LCD source drivers require significant chip or wafer area to achieve high resolution, leading to unacceptable size increases with higher bit resolutions, as the number of resistors and signal lines doubles or quadruples with each bit increase, consuming about 30% of the total area.
Innovation Solution
A two-stage digital-to-analog converter architecture that includes a one-bit serial charge redistribution DAC with high and low reference voltage inputs, a capacitor structure, and switching circuits to provide a high-resolution output while minimizing area usage, using a voltage selector to set reference voltages and a Code Expanding & Decision logic to control the charge redistribution process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional R-type DAC architecture is used to increase resolution, then output precision is improved, but chip area increases proportionally (4x area for each 1-bit increase)
Solution Approach 1:
The patent divides the conventional single-stage DAC into two cascaded stages: a coarse DAC (first digital-to-analog converter) and a fine DAC (second digital-to-analog converter). The coarse DAC handles the most significant bits while the fine DAC handles the least significant bits, allowing each stage to use fewer components than a single high-resolution DAC would require, thereby reducing total chip area while maintaining high output precision.
Solution Approach 2:
The patent introduces a temporal dimension by using sequential operation modes (coarse conversion phase followed by fine conversion phase) rather than simultaneous operation. This allows the same physical resources to be reused across different time periods for different resolution requirements, effectively reducing the spatial footprint on the chip.
2Measurement precision
If number of bits in DAC input is increased to provide high-resolution output, then output precision is improved, but number of resistors and signal lines doubles with each bit increase
Solution Approach 1:
The patent segments the bit-processing function across two DAC stages, where the coarse DAC processes the most significant bits and the fine DAC processes the least significant bits. This segmentation reduces the number of resistors and signal lines required in each individual stage compared to a single high-resolution DAC, as each stage operates with a lower bit-width requirement.
Solution Approach 2:
The patent employs periodic action by operating the two-stage DAC in sequential phases: first the coarse DAC converts the most significant bits, then the fine DAC converts the least significant bits. This periodic, time-division approach allows the system to achieve high-resolution output without requiring all high-resolution components to be present and active simultaneously, thereby reducing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the area required for high-resolution DACs by at least 50% compared to conventional designs, making it suitable for high-speed, large-panel displays by breaking down the DAC functionality into coarse and fine output stages and incorporating gamma correction and offset cancellation.
Implementation Method 1
a first capacitor coupled between a first capacitor charging node and the low reference voltage input node
Implementation Method 2
a second switching circuit for coupling the first capacitor charging node to the charge collection node during charge redistribution cycles that follow the first capacitor charge cycles for charge redistribution with the termination capacitor
Data Source
AI summary
A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage. A voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.