LCD Source Driver Timing Alignment With Automatic De-Skew
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Solution Overview
Problem
Conventional LCDs lack automatic de-skew capability due to varying signal transmission path lengths and differences in toggle rates, ground shielding, and driving capabilities, leading to phase differences and inferior display quality, especially in high-frequency applications.
Innovation Solution
A source driving device with automatic de-skew capability, comprising a data signal delay module, setup time register, hold time register, first and second signal delay units, logic circuit, and data register, which includes variable delay circuits and switches to adjust signal delays and generate control signals for harmonizing data and clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the LCD panel size and resolution are increased to meet user demands, then the display quality and resolution are improved, but the signal transmitting path length increases causing greater signal skew and phase deviation
Solution Approach 1:
The patent implements dynamic delay adjustment through variable delay circuits that can be programmed to provide different delay amounts. The delay amount is dynamically adjusted based on the detected phase deviation, allowing the system to adapt to different signal path lengths and maintain proper synchronization across various LCD panel sizes and resolutions.
Solution Approach 2:
The patent employs a feedback mechanism where the phase relationship between data signals and clock signals is continuously monitored. Based on this feedback, the system automatically adjusts the delay amounts to correct phase deviations, enabling automatic de-skew capability that maintains display quality regardless of signal path length variations.
2Adaptability or versatility
If different source driving devices are used with varying toggle rates and driving capabilities, then the system can adapt to different performance requirements, but the signal delays become inconsistent causing phase deviation
Solution Approach 1:
The patent changes the delay parameter dynamically by programming different delay amounts into the variable delay circuits. This allows the system to compensate for differences in toggle rates and driving capabilities across various source driving devices, maintaining reliable signal synchronization despite hardware variations.
Solution Approach 2:
The system transitions from static fixed delays to dynamic programmable delays, allowing real-time adjustment of signal timing to match the specific characteristics of different source driving devices, thereby maintaining synchronization reliability across diverse hardware configurations.
3Device complexity
If fixed phase relationships and set-up/hold times are used in conventional LCDs, then the circuit design is simple, but the system cannot compensate for signal skew leading to inferior display quality
Solution Approach 1:
The patent replaces static fixed delays with dynamic programmable delay circuits that can be adjusted based on actual signal conditions. This adds complexity to the circuit design but enables automatic compensation for signal skew, significantly improving display quality through adaptive timing adjustment.
Solution Approach 2:
The system implements self-adjustment capability where the source driving device automatically detects and corrects its own timing issues without external intervention. The programmable delay circuits are configured to compensate for signal path variations, allowing the system to self-correct timing deviations and maintain optimal display performance.
Data Source
AI summary
A source driver with an automatic de-skew capability is configured to receive a data signal and a clock signal from a timing controller, which are configured to drive a liquid crystal display panel. The source driver includes a signal delay unit, a setup time register, a hold time register, a first signal delay unit, a second delay unit and a logic circuit. In one embodiment of the present disclosure, the first data delay signal is configured to sample the second clock delay signal and the second data delay signal is configured to sample the first clock delay signal.