LCD Source Driver Output Buffer Polarity Control
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Solution Overview
Problem
In liquid crystal display (LCD) technology, the use of long-term direct current can cause ion impurities to form residual fields, leading to image retention, and existing source drivers face challenges in improving charging speed and reducing output loading, particularly with increasing resolution and frame rate, due to the presence of multiplexers which reduce the slew rate of output buffers.
Innovation Solution
A source driver configuration that includes a plurality of output buffers, each with an input circuit, output circuits, a first multiplexer, a second multiplexer, and a demultiplexer, which generate and distribute control signals and reference voltages to manage the polarity and impedance of data lines effectively, reducing output loading and enhancing driving capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiplexers are added to swap polarities or set data lines in Hi-Z state, then polarity control capability is improved, but output loading of output buffers increases and slew rate decreases
Solution Approach 1:
The output buffer is divided into multiple independent output circuits (first output circuit, second output circuit, third output circuit) that can be independently controlled. Each output circuit can be selectively enabled or disabled through separate control signals, allowing the buffer to serve multiple data lines with different polarity requirements without requiring multiplexers at each output stage.
Solution Approach 2:
The single output buffer is designed to perform multiple functions by controlling different output circuits to drive different data lines (first data line, second data line, third data line) with different polarity states. The buffer can simultaneously provide positive polarity, negative polarity, and high-impedance states to different data lines through the selective activation of output circuits.
2Speed
If output loading is reduced to improve slew rate, then charging speed is improved, but polarity switching capability may be compromised
Solution Approach 1:
The output buffer employs dynamic control where output circuits are selectively enabled or disabled based on real-time polarity requirements. Control signals dynamically activate only the necessary output circuits for each timing period, reducing the total output loading while maintaining the ability to switch between different polarity states as needed by different data lines.
Data Source
AI summary
An output buffer is provided, which including an input circuit, output circuits, a first multiplexer, a second multiplexer and a demultiplexer. The input circuit is for generating a first control signal and a second control signal according to a feedback signal and an input signal. Each output circuit is controlled by a first gate signal and a second gate signal to provide a corresponding one of output signals. The first multiplexer is for providing the first control signal and the second control signal to one of the output circuits as the first gate signal and the second gate signal, respectively. The second multiplexer is for providing a first reference voltage and a second reference voltage as the first gate signal and the second gate signal, respectively, to other of the output circuits. The demultiplexer is for providing one of the output signals as the feedback signal.