LCD Source Driver Bus Layout With Lock-Check Synchronization
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Solution Overview
Problem
Active matrix liquid crystal displays face challenges in reducing the number of data transfer lines between the timing controller and source drive ICs, which complicates the design and increases complexity due to the need for multiple lines for differential signaling.
Innovation Solution
The implementation of a point-to-point data bus connection between the timing controller and source drive ICs, using N pairs of data bus lines, a lock check line, and a feedback lock check line, allows for serial transfer of a preamble signal and lock signal to synchronize internal clock pulses, reducing the need for additional clock and data transfer lines between adjacent source drive ICs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a multi-drop manner of commonly applying clock and digital video data to source drive ICs is used, then the timing controller can control multiple source drive ICs, but the number of data transfer lines between the timing controller and source drive ICs increases significantly
Solution Approach 1:
The patent merges the clock signal and digital video data into a single serial data stream that is transmitted through one data transfer line. The source drive ICs extract the clock signal from this serialized stream, eliminating the need for separate clock transfer lines and reducing the total number of data transfer lines required to control multiple source drive ICs.
Solution Approach 2:
The single data transfer line serves multiple functions by carrying both clock synchronization information and video data simultaneously. This multi-functional approach allows the same physical connection to perform what previously required separate dedicated lines, thereby reducing overall system complexity.
2Reliability
If mini LVDS interface with differential signals is used for data transfer, then reliable signal transmission is achieved, but at least 14 data transfer lines are necessary to transfer odd and even data
Solution Approach 1:
The patent combines multiple data channels (odd and even data) into a single serialized data stream transmitted through one data transfer line. This merging approach maintains the reliability of differential signaling while reducing the number of physical lines from at least 14 to just one, as the serialized stream encodes all necessary data sequentially.
3Productivity
If cascade connection of source drive ICs is implemented, then sequential sampling of digital video data is enabled, but synchronization of internal clock pulses becomes more difficult to verify
Solution Approach 1:
The patent implements a feedback mechanism where the timing controller monitors the synchronization status of internal clock pulses in each source drive IC and provides appropriate control signals to maintain proper synchronization. This feedback loop enables automatic detection and correction of synchronization issues, making the verification process simpler and more reliable.
Solution Approach 2:
The patent introduces an intermediary synchronization signal that mediates between the timing controller and the cascade-connected source drive ICs. This intermediary signal serves as a reference that facilitates easy verification of clock pulse synchronization across all ICs in the cascade chain, solving the difficulty of detecting and measuring synchronization status.
Data Source
AI summary
A liquid crystal display and a method of driving the same are disclosed. The liquid crystal display includes a timing controller, N source drive integrated circuits (ICs), where N is an integer equal to or greater than 2, N pairs of data bus lines, each of which connects the timing controller to each of the N source drive ICs in a point-to-point manner, a lock check line that connects a first source drive IC of the N source drive ICs to the timing controller and cascade-connects the N source drive ICs to one another, a feedback check line that connects a last source drive IC of the N source drive ICs to the timing controller.