LCD Aperture Ratio via Stacked Gate Lines
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Solution Overview
Problem
The Z-shaped inversion system in liquid crystal displays faces issues with aperture ratio reduction and color distortion due to electrical coupling between pixel electrodes and gate lines, leading to suboptimal display quality and increased power consumption.
Innovation Solution
The solution involves increasing the distance between pixel electrodes and gate lines to minimize electrical coupling, while rearranging the charge order of data voltages to balance the average voltage of R and G liquid crystal cells, thereby reducing color distortion and maintaining a sufficient aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the distance between pixel electrodes and gate lines is increased to reduce electrical coupling, then color distortion is reduced, but aperture ratio decreases
Solution Approach 1:
The patent introduces a third dimension (stacking gate lines vertically) to resolve the spatial conflict between reducing electrical coupling and maintaining aperture ratio. By arranging gate lines G1 and G2 in different vertical layers rather than only horizontal separation, the design reduces coupling between pixel electrodes and gate lines while minimizing the horizontal space consumed, thus preserving aperture ratio.
2Manufacturing precision
If data voltage polarity is inverted in both vertical and horizontal directions (dot inversion system), then image quality improves, but power consumption and heat generation increase
Solution Approach 1:
The patent applies different inversion strategies to different regions: dot inversion is applied to even-numbered data lines (D2, D4, ...) while line inversion is applied to odd-numbered data lines (D1, D3, ...). This localized application of inversion methods maintains image quality benefits where needed while reducing overall power consumption and heat generation compared to universal dot inversion.
3Area of stationary object
If gate lines are positioned close to pixel electrodes to maintain high aperture ratio, then aperture ratio is maintained, but electrical coupling increases causing color distortion
Solution Approach 1:
The patent resolves this contradiction by utilizing the vertical dimension through stacked gate line architecture. Gate line G1 is positioned in a first vertical layer closer to pixel electrodes to maintain aperture ratio, while gate line G2 is positioned in a second vertical layer to provide additional coupling reduction. This three-dimensional arrangement allows both goals to be achieved simultaneously.
4Use of energy by moving object
If Z-shaped inversion system is implemented to reduce data line frequency, then power consumption decreases, but aperture ratio and display quality are compromised
Solution Approach 1:
The patent segments the gate line control into multiple independent gate lines (G1, G2) with different inversion patterns. Even-numbered data lines use dot inversion while odd-numbered data lines use line inversion, allowing the system to achieve the power consumption benefits of reduced frequency operation while maintaining aperture ratio through the segmented, multi-pattern approach.
Data Source
AI summary
A liquid crystal display is disclosed. The liquid crystal display includes a data line arranged in a column direction, a first pixel electrode that is positioned on the left side of the data line on a first line, a second pixel electrode that is positioned on the right side of the data line on the first line, a first gate line that is arranged between the first line and the second line in a line direction perpendicular to the column direction, a second gate line that is arranged between the first line and the second line in the line direction, the second gate line underlying the first gate line, a first thin film transistor that is positioned on the left side of the data line on the first line to supply a first data voltage received from the data line to the first pixel electrode in response to a gate pulse received from the first gate line, and a second thin film transistor that is positioned on the right side of the data line on the first line, crosses the first gate line to be connected to the second pixel electrode, and supplies a second data voltage received from the data line to the second pixel electrode in response to a gate pulse received from the second gate line.