Storage Driving Circuit for LCD Power and Response Optimization
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Solution Overview
Problem
Liquid crystal display (LCD) devices face increased power consumption and slower response times as resolution increases, necessitating a solution to reduce power consumption and enhance response speed.
Innovation Solution
A display device incorporating a storage driving circuit with multiple stages, including a counter charging part, a boosting part, and a holding part, which applies inverted storage voltages to storage lines based on gate signals, optimizing voltage levels and switching elements to reduce power consumption and increase response speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If resolution of LCD devices is increased, then display quality is improved, but power consumption increases
Solution Approach 1:
The storage driving circuit pre-charges the storage line with a first driving voltage before the data driving circuit needs to write data. This preliminary action reduces the voltage difference that needs to be bridged during data writing, thereby reducing the current consumption and power consumption of the display device while maintaining high resolution display quality
2Measurement precision
If resolution of LCD devices is increased, then display quality is improved, but response speed decreases
Solution Approach 1:
By pre-charging the storage line with a first driving voltage that is closer to the data voltage level, the voltage difference during data writing is reduced. This decreases the charging time of the liquid crystal capacitor, thereby improving response speed while maintaining high resolution
Solution Approach 2:
The storage driving circuit dynamically adjusts the storage voltage level based on the data voltage level. When data voltage is high, the storage line is charged to a higher voltage level, and when data voltage is low, the storage line is charged to a lower voltage level. This parameter adjustment optimizes the voltage difference during data writing, reducing charging time and improving response speed
3Speed
If storage voltage is inverted in every frame, then response speed is improved, but horizontal crosstalk occurs
Solution Approach 1:
The storage driving circuit applies different voltage levels to different storage lines at different times. Specifically, the kth storage line is charged to a first driving voltage when the kth gate line is activated, and to a second driving voltage when the (k+2)th gate line is activated. This localized voltage application prevents simultaneous voltage changes across multiple storage lines, thereby preventing horizontal crosstalk while maintaining the benefits of voltage inversion for response speed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively decreases power consumption and increases response speed by synchronizing storage voltage levels with gate signals, preventing horizontal crosstalk and enhancing luminance through improved gray scale voltage range.
Implementation Method 1
a storage line, and a storage driving circuit including a plurality of stages to apply a plurality of storage voltages, which are inverted in every frame, to the storage lines, respectively
Implementation Method 2
The liquid crystal layer has liquid crystals having dielectric anisotropy. The alignment of the liquid crystals of the liquid crystal layer varies in response to an electric field applied thereto, changing the light transmittance of the liquid crystal layer and displaying an image
Data Source
AI summary
A display device includes a display panel, a gate driving circuit, a data driving circuit, and a storage driving circuit. The storage driving circuit includes a plurality of stages to apply a plurality of storage voltages, which are inverted in every frame, to the storage lines, respectively. A kth stage of the stages includes a counter charging part, a boosting part and a holding part. The counter charging part applies a first driving voltage to a kth storage line based on a kth gate signal. The boosting part applies a second driving voltage to the kth storage line based on a (k+2)th gate signal. The holding part applies a storage voltage to the kth storage line based on a (k+1)th gate signal during one frame. The level of the storage voltage corresponds to the second driving voltage.