LCD Sub-Pixel Storage Line Configuration for IR Drop Reduction

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Solution Overview

Problem

Liquid crystal display (LCD) devices experience image quality degradation due to voltage drops in voltage wiring, leading to undesirable visual artifacts like afterimage and flicker, especially when data signals are applied to sub-pixel electrodes with different voltage levels.

Innovation Solution

The LCD device incorporates a configuration with separate storage lines receiving different storage voltages, where the second storage line is not adjacent to the first sub-pixel electrode, reducing voltage level variations and minimizing IR drop effects, and includes a third storage line with equal voltage levels to the first storage line, overlapping with the first sub-pixel electrode.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Illumination intensity

If data signals are applied to sub-pixel electrodes with different voltage levels to improve visibility, then display quality is improved, but voltage drops in wiring cause visual artifacts like afterimage and flicker

Engineering Contradiction:
ImprovevisibilityVSAvoidimage quality stability
Core Design Contradiction:
Illumination intensityVSReliability

Solution Approach 1:

The pixel is divided into two separate sub-pixel electrodes (first and second sub-pixel electrodes) with independent voltage control through separate transistors and storage lines, allowing independent voltage level adjustment for each sub-pixel to improve visibility while maintaining stable voltage delivery

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Storage lines with storage capacitors are introduced as intermediary elements between the data lines/transistors and the sub-pixel electrodes. These storage lines hold stable voltage levels and compensate for voltage drops during the display period, preventing visual artifacts while maintaining the ability to apply different voltage levels to different sub-pixels

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If storage lines are placed adjacent to both sub-pixel electrodes to reduce voltage drops, then voltage stability is improved, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improvevoltage stabilityVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The storage line configuration is optimized locally for each sub-pixel electrode. The first storage line is adjacent to the first sub-pixel electrode, while the second storage line is spaced apart and adjacent to the second sub-pixel electrode. This localized arrangement provides voltage stability where needed while avoiding unnecessary complexity in other areas

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The storage lines are arranged in different spatial positions and orientations relative to the sub-pixel electrodes. The first storage line overlaps the first sub-pixel electrode, while the second storage line is spaced apart and overlaps the second sub-pixel electrode, creating a distributed three-dimensional voltage compensation network that reduces complexity compared to a uniform arrangement

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10852612B2Liquid crystal display device
Publication Date: 2020.12.01 SAMSUNG DISPLAY CO LTD
  • US10852612B2 patent drawing
  • US10852612B2 patent drawing
  • US10852612B2 patent drawing

AI summary

A liquid crystal display device includes a liquid crystal layer between first and second substrate. The first substrate includes a first and second sub-pixel areas. A first sub-pixel electrode is on the first substrate in the first sub-pixel area, and a first transistor is connected to a gate line, data line, and first sub-pixel electrode on the first substrate. A second sub-pixel electrode is on the first substrate in the second sub-pixel area, and a second transistor is connected to the gate line, the first transistor, and the second sub-pixel electrode. A first storage line is adjacent to one side of the first sub-pixel electrode. A second storage line is spaced from the first storage line and is adjacent to one side of the second sub-pixel electrode. A third transistor is connected to the gate line, second transistor, and second storage line.