LCD Display Substrate Layout for Higher Transmittance
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Solution Overview
Problem
Existing liquid crystal display (LCD) panels with advanced super dimensional switching (ADS) display mode face limitations in transmittance and power consumption due to pixel structure constraints, particularly in high aperture ratio and high resolution applications.
Innovation Solution
The display substrate design includes a base substrate with data and gate lines, a first electrode layer, and transistors, where the gate electrodes are spaced apart from gate lines, and employs protruding structures and spacers to improve film layer flatness and transmittance without increasing process complexity, using a high aperture ratio (HADS) display mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the gate electrode is positioned directly over the gate line to simplify structure, then device complexity is reduced, but film layer flatness deteriorates causing alignment issues and reduced transmittance
Solution Approach 1:
The patent positions the gate electrode laterally offset from the gate line in the planar dimension rather than directly above it, creating a spatial separation that prevents film layer wrinkling while maintaining electrical connection through the transistor structure. This dimensional arrangement resolves the conflict between structural simplicity and film flatness.
Solution Approach 2:
The transistor structure acts as an intermediary element that connects the gate electrode to the gate line without requiring direct overlap. The gate electrode connects to the transistor, which in turn connects to the gate line, allowing the film layer to remain flat while maintaining electrical connectivity.
2Loss of energy
If the data line is positioned closer to the pixel electrode to reduce aperture loss, then transmittance is improved, but capacitance coupling between data line and pixel electrode increases causing display defects
Solution Approach 1:
The patent utilizes the vertical dimension by positioning the data line in a lower film layer while the pixel electrode is in an upper film layer. This vertical separation reduces parasitic capacitance coupling while allowing the data line to remain close to the pixel electrode horizontally, thus maintaining high transmittance without the harmful capacitive effects.
Solution Approach 2:
The patent segments the conductor layers into different vertical levels, with data lines in one layer and pixel electrodes in another layer. This segmentation allows close horizontal proximity for optical performance while maintaining vertical separation for electrical isolation, resolving the contradiction between transmittance and capacitance coupling.
3Loss of energy
If the aperture ratio is increased to improve transmittance, then transmittance is improved, but pixel structure constraints limit further optimization
Solution Approach 1:
The patent moves conductive elements (data lines, gate lines) to different vertical layers, freeing up horizontal space in the pixel aperture area. This vertical stratification allows for larger aperture ratios without increasing in-plane structural complexity, as the routing is accomplished in the vertical dimension.
Solution Approach 2:
The multi-layer conductor structure serves multiple functions simultaneously: it provides electrical connectivity, reduces parasitic capacitance, and maximizes aperture area. This universal approach allows the same structural framework to achieve multiple optimization goals without proportionally increasing complexity.
Data Source
AI summary
A display substrate and a display apparatus are provided. The display substrate includes a base substrate and data lines, gate lines, a first electrode layer, and transistors. The first electrode layer is on a side of the data lines away from the base substrate; each transistor includes a gate electrode, a first electrode and a second electrode, second electrodes of the transistors are electrically connected to the first electrode layer. The gate lines are located on a side of the data lines away from the base substrate, the gate electrodes of the transistors are arranged on the same layer as the data lines, and an orthographic projection of the gate electrode of at least one transistor on the base substrate is spaced apart from an orthographic projection of the gate line.