LCD Timing Control Unit Dynamic Clock Frequency Adjustment
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Solution Overview
Problem
Existing LCD devices consume the same power in both normal and non-signal image driving states due to the use of a fixed oscillator clock, leading to inefficient power management.
Innovation Solution
Incorporating a frequency divider within the timing control unit to reduce the clock frequency by half and a mode selection part to change the driving mode of internal logic circuits, allowing for distinct power management between normal and non-signal image states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If a fixed oscillator clock is used to drive logic circuits in both normal and non-signal image driving states, then the device structure remains simple, but power consumption cannot be reduced in non-signal states
Solution Approach 1:
The patent applies dynamics by making the clock frequency adjustable rather than fixed. The oscillator clock frequency is dynamically changed based on the driving state: using a first clock frequency in normal image driving state and a second clock frequency (lower than the first) in non-signal image driving state. This dynamic frequency adjustment enables power reduction in non-signal states while maintaining simple device structure.
2Productivity
If the same clock frequency is used for all logic circuits, then the control logic is simple, but power management efficiency deteriorates
Solution Approach 1:
The patent applies local quality by differentiating clock frequency allocation based on functional requirements. Different logic circuits receive different clock frequencies according to their operational needs: essential circuits continue operating at the first clock frequency while non-essential circuits are switched to the second lower frequency or stopped in non-signal states. This selective frequency assignment improves power management efficiency with minimal control logic complexity.
Data Source
AI summary
The present invention provides a LCD device including: a timing control unit; an oscillator which is included in the timing control unit and generates a clock frequency; a frequency divider which is included in the timing control unit and reduces the clock frequency supplied from the oscillator by dividing the clock frequency by at least 2; and a mode selection part which is included in the timing control unit and changes at least one driving mode of internal logic circuits by using the divided clock frequency supplied from the frequency divider.