Timing Controller Delay Compensation for LCD Signal Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing Liquid Crystal Displays (LCDs) face synchronization issues due to delay in Low Voltage Differential Signal (LVDS) output signals between the timing controller and data drive ICs, caused by varying cable resistance and parasitic components, leading to abnormal output and requiring costly redesigns of Printed Circuit Boards (PCBs).
Innovation Solution
A timing controller with a delay compensation unit that measures and compensates for signal delays between the timing controller and data drive ICs, using a recombined circuit based on calculated delay values to synchronize LVDS signals, thereby ensuring synchronized data transfer across all data drive ICs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the timing controller outputs LVDS signals through cables and source PCB to data drive ICs, then the LCD can function with standard interface connections, but signal delay occurs due to varying cable resistance and parasitic components
Solution Approach 1:
The patent applies preliminary action by measuring and calculating delay compensation values during the manufacture stage of the liquid crystal display panel. These compensation values are stored in a delay compensation unit that reconfigures circuits before actual operation, preventing signal synchronization issues from occurring during normal use without requiring real-time adjustment mechanisms.
2Reliability
If the LCD redesigns the source PCB to solve signal delay, then signal synchronization can be improved, but development time and cost increase
Solution Approach 1:
The patent changes the parameter of delay compensation from a fixed PCB design parameter to an adjustable circuit configuration parameter. By storing multiple delay compensation values and reconfiguring circuits based on measured delays, the system achieves signal synchronization without requiring PCB redesign, thereby reducing development time and cost while maintaining reliability.
3Measurement precision
If the LCD uses fixed termination resistance value and output current, then the mini-LVDS output signal level can be controlled, but signal delay cannot be compensated
Solution Approach 1:
The patent introduces dynamics by making the delay compensation value adjustable rather than fixed. The delay compensation unit can reconfigure circuits based on different delay compensation values stored in memory, allowing the system to adapt to varying signal delay conditions while maintaining precise control over output signal levels through fixed termination resistance.
4Reliability
If the timing controller individually compensates delay for each data drive IC, then signal synchronization is achieved, but circuit complexity increases
Solution Approach 1:
The patent applies segmentation by providing separate delay compensation circuits for each mini-LVDS output terminal corresponding to each data drive IC. Each compensation circuit can be independently configured with appropriate delay compensation values, allowing individualized delay compensation for each channel while maintaining modularity and manageable complexity through standardized circuit designs.
Data Source
AI summary
A timing controller and a Liquid Crystal Display (LCD) using the same are discussed. The timing controller according to an embodiment includes a reception unit which receives a video signal and a timing signal from a system; a control signal generation unit which generates a gate control signal and a data control signal with the timing signal, and outputs the gate control signal and the data control signal to a gate driver and a data driver, respectively; an image signal generation unit which realigns the video signal to output a realigned image signal; and a delay compensation unit which performs delay compensation for the realigned image signal with a circuit recombined according to a delay compensation value between each data drive Integrated Chip (IC) of the data driver and the image signal generation unit, and outputs the delay-compensated image signal to each data drive IC.