LCD Timing Controller Memory Clock Control
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Solution Overview
Problem
In liquid crystal display (LCD) devices, the continuous toggling of the memory clock leads to high electric current consumption and potential overheating of the timing controller, complicating individual memory control.
Innovation Solution
A data comparing and blank time detecting device generates a flag signal to stop the memory clock when current data is the same as previous data or during blank times, allowing intermittent operation of the memory clock, synchronized with a data synchronizer to manage data input and reduce unnecessary memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory clock continuously toggles at high frequency to ensure data is always available in the timing controller, then data availability is improved, but electric current consumption increases significantly
Solution Approach 1:
The memory clock is changed from continuous toggling to periodic operation. The clock signal is generated only during periods when data changes occur (active data periods) and suspended during blank periods and data hold periods when data remains unchanged. This periodic activation pattern maintains data availability when needed while dramatically reducing power consumption during periods when data does not change.
Solution Approach 2:
The memory clock operation is made dynamic rather than static. The clock frequency and presence are adjusted in real-time based on the actual data change detection status. When data changes are detected, the clock operates at full frequency; when no changes occur, the clock is suspended or reduced, creating a dynamic adaptation to operational needs that balances reliability and energy efficiency.
2Speed
If the memory clock continuously toggles at high frequency to maintain data readiness, then data access speed is improved, but the timing controller overheats and reliability degrades
Solution Approach 1:
The continuous high-frequency clock toggling is replaced with periodic clock generation that occurs only during active data periods. By suspending the clock during blank periods and data hold periods, the thermal load on the timing controller is significantly reduced while maintaining full data access speed when actual data changes occur, preventing overheating without sacrificing performance when needed.
3Reliability
If the memory clock continuously toggles to ensure data is always ready, then data availability is improved, but individual control of multiple memories becomes difficult
Solution Approach 1:
Data change detection is performed in advance to determine when clock generation should occur. The system proactively identifies periods when data changes will occur and schedules clock generation accordingly, rather than continuously operating the clock. This preliminary detection and scheduling approach enables precise control over multiple memory operations, improving both data availability and control flexibility by coordinating clock generation with actual data change events.
Data Source
AI summary
A display device including a display panel having a plurality of data lines and a plurality of gate lines disposed cross-wisely, a timing controller, the timing controller including a data comparing and blank time detecting device comparing whether current data and previous data are same and detecting a blank time in which no data inputs to generate a flag signal for indicating the blank time and a data keeping time in which a data same with the previous data is inputted, a memory control signal generator generating a memory clock, and stopping the generation of the memory clock when the flag signal is generated, a memory which is operated by the memory clock intermittently by the flag signal, and a data synchronizer delaying the data in time for treating operation of the data comparing and blank time detecting device and the memory control signal generator to synchronize the data inputted to the memory with the memory clock, and a data drive circuit converting data from the memory into a data voltage and supplying to the data lines, and a gate drive circuit supplying a scan pulse to the gate lines.