LCD Timing Controller Signal Extension for Flicker Reduction
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Solution Overview
Problem
Liquid crystal display devices experience reduced charging time for pixel electrodes during abnormal data enable signal states, leading to potential flickering and degradation of display quality due to insufficient charging of pixel electrodes.
Innovation Solution
A liquid crystal display device and method that maintains at least one of the gate or source output enable signals at a predetermined level for at least two cycles of the gate shift clock, ensuring sufficient charging time for pixel electrodes by preventing overlap of gate voltage signals and suspending polarity inversion of data voltage signals during abnormal data enable signal states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the data enable signal width is reduced during abnormal operation, then the response time is reduced, but the charging time of pixel electrodes becomes insufficient leading to display quality degradation
Solution Approach 1:
The gate output enable signal is dynamically adjusted based on the detected abnormal state of the data enable signal. When an abnormal narrow width is detected, the gate output enable signal is extended to maintain sufficient charging time for pixel electrodes, while returning to normal width when the data enable signal恢复正常. This dynamic adaptation resolves the contradiction between fast response and reliable display quality.
Solution Approach 2:
The patent changes the temporal parameter (width) of the gate output enable signal in response to abnormal operating conditions. By extending the pulse width of the gate output enable signal during abnormal data enable signal states, the system ensures sufficient charging time for pixel electrodes while maintaining normal operation during standard conditions, thus resolving the contradiction between speed and reliability.
2Productivity
If the gate voltage signal width is reduced to match the abnormal data enable signal, then the operating speed increases, but the pixel electrode charging becomes insufficient causing flickering
Solution Approach 1:
The patent applies preliminary anti-action by detecting the abnormal data enable signal state in advance and preemptively adjusting the gate output enable signal width to prevent insufficient charging. This compensatory extension of the gate signal prevents the harmful effect of flickering before it can occur, while maintaining normal operating speed during standard conditions.
3Stability of the object's composition
If polarity inversion is continuously applied during abnormal operation, then the liquid crystal response is maintained, but the charging time is further reduced causing display abnormalities
Solution Approach 1:
The patent modifies the periodic polarity inversion action by suspending it during abnormal data enable signal states. By conditionally disabling the polarity inversion feature only when abnormal narrow data enable signals are detected, the system maintains sufficient charging time for pixel electrodes while preserving liquid crystal response stability during normal periodic operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures that pixel electrodes are adequately charged, reducing flickering and improving display quality while minimizing liquid crystal deterioration, even during abnormal operating conditions.
Implementation Method 1
a voltage applied between the electrodes induces an electric field across the layer of liquid crystal. The alignment of the liquid crystal molecules changes based on the intensity of the induced electric field, thereby changing the light transmissivity of the LCD device.
Data Source
AI summary
A liquid crystal display device is disclosed. The disclosed liquid crystal display includes a liquid crystal panel having a plurality of data lines and a plurality of gate lines. The disclosed liquid crystal display device also includes a timing controller to receive a data enable signal and a data signal, and to output a gate shift clock, a gate output enable signal, and a source output enable signal, wherein at least one of the gate output enable signal and the source output enable signal is maintained at a predetermined level for at least two cycles of the gate shift clock based on a state of the data enable signal. In addition, the disclosed liquid crystal display device includes a source driver to supply the data lines with corresponding data voltage signals based on the data signal and the source output enable signal, and a gate driver to supply the gate lines with corresponding gate voltage signals based on the gate output enable signal.