Timing Controller Synchronization for LCD Display Defects
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Solution Overview
Problem
In multi-chip driving devices for liquid crystal display (LCD) systems, synchronization issues between timing controllers lead to display defects such as abnormal image display, waterfall defects, and charge rate defects, particularly when displaying high-resolution videos and 3D images.
Innovation Solution
A method of synchronizing a driving device using a master timing controller and slave timing controllers, where synchronization signals are generated using data enable signals to ensure synchronized operation, reducing display defects by controlling the synchronization between master and slave timing controllers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a multi-chip structure with two or more timing controllers is used for high-speed frame driving, then the frame rate can be increased to 60 Hz or 120 Hz, but synchronization issues between chips occur leading to display defects
Solution Approach 1:
The master timing controller generates a synchronization signal based on its own data enable signal and sends it to slave timing controllers. The slave timing controllers use this synchronization signal to align their operation with the master controller, creating a feedback mechanism that ensures synchronized operation across all chips and prevents display defects
Solution Approach 2:
The timing control function is divided into multiple independent timing controllers (master and slave) that can operate separately but are coordinated through the synchronization signal. This segmentation allows each controller to handle specific display blocks independently while maintaining overall system synchronization
2Manufacturing precision
If high-speed frame driving method is used to insert motion interpolation frames, then motion blur is decreased, but synchronization between timing controllers becomes more critical and difficult to maintain
Solution Approach 1:
The synchronization signal acts as an intermediary between the master and slave timing controllers. It mediates the coordination between chips, ensuring that even during high-speed frame driving with motion interpolation, all controllers operate in sync without requiring complex direct communication between each pair of controllers
3Adaptability or versatility
If frame image is divided into left-eye and right-eye images for 3D display, then 3D image capability is achieved, but synchronization requirements between chips increase leading to waterfall defects and charge rate defects
Solution Approach 1:
The synchronization signal provides continuous feedback to slave timing controllers to maintain precise alignment when handling divided left-eye and right-eye image data. This feedback mechanism ensures that the alternating display of stereoscopic frames remains synchronized across all display blocks, preventing waterfall and charge rate defects
Data Source
AI summary
A display apparatus includes a driving part and a display panel. The driving part includes a master timing controller and at least one slave timing controller synchronized with the master timing controller using a first data enable signal received by the master timing controller and a second data enable signal received by the slave timing controller. The display panel displays a first image on a first display block, and displays a second image on a second display block using the master timing controller.