Timing Controller Vertical Enable Signal for LCD Flickering
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Solution Overview
Problem
Liquid crystal display (LCD) devices face issues with image flickering and abnormal display when changing frame frequency due to external noise interference and power consumption limitations, leading to restricted usage time in portable devices.
Innovation Solution
A timing controller with a vertical enable signal generator that enables or disables gate and data control signal generators based on signal quality, preventing flickering and maintaining previous frame data during frequency changes, and optimizing power consumption by adjusting frame frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If frame frequency is changed to optimize power consumption, then power consumption is reduced, but image flickering and abnormal display occur
Solution Approach 1:
The patent implements dynamic frame frequency adjustment by enabling the system to switch between different frame frequencies (e.g., 60Hz and 40Hz) based on operational requirements. The timing controller dynamically modifies the frame frequency signal to optimize power consumption while maintaining display stability through coordinated control of gate and data drivers.
Solution Approach 2:
The patent applies preliminary action by pre-configuring the timing controller to coordinate the operation of gate drivers and data drivers before frame frequency changes occur. This ensures that signal synchronization is maintained during transitions, preventing image flickering and abnormal display while enabling power optimization.
2Ease of operation
If TTL signaling is used for signal transmission, then ease of operation is improved, but susceptibility to external noise increases
Solution Approach 1:
The patent introduces an intermediary mechanism in the timing controller that processes and conditions signals before they are transmitted to the gate and data drivers. This intermediary processing stage filters and stabilizes signals, reducing susceptibility to external noise while maintaining the simplicity of TTL signaling operation.
3Object-affected harmful factors
If LVDS signaling is used for signal transmission, then resistance to external noise is improved, but device complexity increases
Solution Approach 1:
The patent implements a simplified signal transmission approach by using TTL signaling with enhanced timing control and signal conditioning within the timing controller. This creates a functional equivalent to LVDS noise resistance without requiring the complex differential signal pairs and associated hardware, thereby reducing device complexity while maintaining noise immunity.
4Duration of action of moving object
If frame frequency is reduced to extend usage time, then duration of action is improved, but image display quality deteriorates
Solution Approach 1:
The patent enables dynamic switching between different frame frequencies (60Hz for high quality, 40Hz for extended usage time) based on operational needs. The timing controller dynamically adjusts the frame frequency signal and coordinates driver operations to maintain image display quality even at reduced frequencies, preventing flickering and abnormal display.
Solution Approach 2:
The patent changes the frame frequency parameter from a fixed value to a variable parameter that can be adjusted between 60Hz and 40Hz. This parameter change is accompanied by synchronized adjustments in gate and data driver timing to ensure that image display quality is maintained across different frequency settings, extending usage time without compromising reliability.
Data Source
AI summary
A liquid crystal display device includes a liquid crystal panel, gate and data drivers providing the liquid crystal panel with gate and data signals, and a timing controller receiving input signals that include an image signal, a sync signal, a data enable signal and a clock signal, wherein the timing controller includes a gate control signal generator controlling the gate driver, a data control signal generator controlling the data driver, a data processor supplying the image signal to the data driver, and a vertical enable signal generator generating a vertical enable signal according to the data enable signal and controlling the gate control signal generator and the data control signal generator.